forked from OSchip/llvm-project
92 lines
3.4 KiB
YAML
92 lines
3.4 KiB
YAML
# RUN: llc -mtriple=arm-none-eabi -run-pass=arm-cp-islands %s -o - | FileCheck %s
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#
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# This checks alignment of a new block when a big basic block is split up.
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#
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--- |
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; ModuleID = '<stdin>'
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source_filename = "<stdin>"
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "arm-arm--eabi"
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declare i32 @llvm.arm.space(i32, i32) #0
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define dso_local i32 @ARM(i64* %LL, i32 %A.coerce) local_unnamed_addr #1 {
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entry:
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%S = alloca half, align 2
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%tmp.0.extract.trunc = trunc i32 %A.coerce to i16
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%0 = bitcast i16 %tmp.0.extract.trunc to half
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store volatile half 0xH3C00, half* %S, align 2
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store volatile i64 4242424242424242, i64* %LL, align 8
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%1 = call i32 @llvm.arm.space(i32 8920, i32 undef)
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%S.0.S.0.570 = load volatile half, half* %S, align 2
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%add298 = fadd half %S.0.S.0.570, 0xH2E66
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store volatile half %add298, half* %S, align 2
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%2 = call i32 @llvm.arm.space(i32 1350, i32 undef)
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%3 = bitcast half %add298 to i16
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%tmp343.0.insert.ext = zext i16 %3 to i32
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ret i32 %tmp343.0.insert.ext
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}
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attributes #0 = { nounwind }
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attributes #1 = { minsize nounwind optsize "target-features"="+crc,+crypto,+dsp,+fp-armv8,+fullfp16,+hwdiv,+hwdiv-arm,+neon,+ras,+strict-align,-thumb-mode" }
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...
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---
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name: ARM
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0' }
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frameInfo:
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stackSize: 4
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maxAlignment: 2
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maxCallFrameSize: 0
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stack:
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- { id: 0, name: S, offset: -2, size: 2, alignment: 2, stack-id: default, local-offset: -2 }
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constants:
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- id: 0
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value: i32 1576323506
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alignment: 4
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- id: 1
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value: i32 987766
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alignment: 4
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- id: 2
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value: half 0xH2E66
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alignment: 2
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#CHECK: B %[[BB4:bb.[0-9]]]
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#CHECK: bb.{{.}} (align 4):
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#CHECK: successors:
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#CHECK: CONSTPOOL_ENTRY {{.}}, %const.{{.}}, 4
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#CHECK: bb.{{.}} (align 4):
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#CHECK: successors:
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#CHECK: CONSTPOOL_ENTRY {{.}}, %const.{{.}}, 4
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#CHECK: bb.{{.}} (align 2):
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#CHECK: successors:
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#CHECK: CONSTPOOL_ENTRY {{.}}, %const.{{.}}, 2
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#CHECK: [[BB4]].entry (align 4):
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body: |
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bb.0.entry:
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liveins: $r0
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$sp = frame-setup SUBri $sp, 4, 14, $noreg, $noreg
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frame-setup CFI_INSTRUCTION def_cfa_offset 4
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renamable $s0 = FCONSTH 112, 14, $noreg
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renamable $r1 = LDRcp %const.0, 0, 14, $noreg :: (load (s32) from constant-pool)
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renamable $r2 = LDRcp %const.1, 0, 14, $noreg :: (load (s32) from constant-pool)
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VSTRH killed renamable $s0, $sp, 1, 14, $noreg :: (volatile store (s16) into %ir.S)
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STRi12 killed renamable $r2, renamable $r0, 4, 14, $noreg :: (volatile store (s32) into %ir.LL + 4)
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renamable $s0 = VLDRH %const.2, 0, 14, $noreg :: (load (s16) from constant-pool)
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STRi12 killed renamable $r1, killed renamable $r0, 0, 14, $noreg :: (volatile store (s32) into %ir.LL, align 8)
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dead renamable $r0 = SPACE 8920, undef renamable $r0
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renamable $s2 = VLDRH $sp, 1, 14, $noreg :: (volatile dereferenceable load (s16) from %ir.S)
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renamable $s0 = VADDH killed renamable $s2, killed renamable $s0, 14, $noreg
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VSTRH renamable $s0, $sp, 1, 14, $noreg :: (volatile store (s16) into %ir.S)
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renamable $r0 = VMOVRH killed renamable $s0, 14, $noreg
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dead renamable $r1 = SPACE 1350, undef renamable $r0
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$sp = ADDri $sp, 4, 14, $noreg, $noreg
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MOVPCLR 14, $noreg, implicit killed $r0
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...
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