forked from OSchip/llvm-project
175 lines
4.7 KiB
LLVM
175 lines
4.7 KiB
LLVM
; RUN: llc -mtriple=arm64-apple-ios %s -o - | FileCheck %s --check-prefixes=CHECK-NOAUTH,CHECK
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; RUN: llc -mtriple=arm64-apple-ios -mcpu=apple-a13 %s -o - | FileCheck %s --check-prefixes=CHECK-NOAUTH,CHECK
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; RUN: llc -mtriple=arm64e-apple-ios %s -o - | FileCheck %s --check-prefixes=CHECK-AUTH,CHECK
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; Important details in prologue:
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; * x22 is stored just below x29
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; * Enough stack space is allocated for everything
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define swifttailcc void @simple(i8* swiftasync %ctx) "frame-pointer"="all" {
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; CHECK-LABEL: simple:
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; CHECK: orr x29, x29, #0x100000000000000
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; CHECK: sub sp, sp, #32
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; CHECK: stp x29, x30, [sp, #16]
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; CHECK-NOAUTH: str x22, [sp, #8]
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; CHECK-AUTH: add x16, sp, #8
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; CHECK-AUTH: movk x16, #49946, lsl #48
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; CHECK-AUTH: mov x17, x22
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; CHECK-AUTH: pacdb x17, x16
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; CHECK-AUTH: str x17, [sp, #8]
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; CHECK: add x29, sp, #16
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; CHECK: .cfi_def_cfa w29, 16
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; CHECK: .cfi_offset w30, -8
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; CHECK: .cfi_offset w29, -16
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;[...]
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; CHECK: ldp x29, x30, [sp, #16]
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; CHECK: and x29, x29, #0xefffffffffffffff
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; CHECK: add sp, sp, #32
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ret void
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}
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define swifttailcc void @more_csrs(i8* swiftasync %ctx) "frame-pointer"="all" {
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; CHECK-LABEL: more_csrs:
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; CHECK: orr x29, x29, #0x100000000000000
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; CHECK: str x23, [sp, #-32]!
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; CHECK: stp x29, x30, [sp, #16]
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; CHECK-NOAUTH: str x22, [sp, #8]
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; CHECK-AUTH: add x16, sp, #8
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; CHECK-AUTH: movk x16, #49946, lsl #48
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; CHECK-AUTH: mov x17, x22
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; CHECK-AUTH: pacdb x17, x16
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; CHECK-AUTH: str x17, [sp, #8]
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; CHECK: add x29, sp, #16
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; CHECK: .cfi_def_cfa w29, 16
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; CHECK: .cfi_offset w30, -8
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; CHECK: .cfi_offset w29, -16
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; CHECK: .cfi_offset w23, -32
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; [...]
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; CHECK: ldp x29, x30, [sp, #16]
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; CHECK: ldr x23, [sp], #32
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; CHECK: and x29, x29, #0xefffffffffffffff
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call void asm sideeffect "", "~{x23}"()
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ret void
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}
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define swifttailcc void @locals(i8* swiftasync %ctx) "frame-pointer"="all" {
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; CHECK-LABEL: locals:
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; CHECK: orr x29, x29, #0x100000000000000
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; CHECK: sub sp, sp, #64
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; CHECK: stp x29, x30, [sp, #48]
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; CHECK-NOAUTH: str x22, [sp, #40]
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; CHECK-AUTH: add x16, sp, #40
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; CHECK-AUTH: movk x16, #49946, lsl #48
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; CHECK-AUTH: mov x17, x22
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; CHECK-AUTH: pacdb x17, x16
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; CHECK-AUTH: str x17, [sp, #40]
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; CHECK: add x29, sp, #48
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; CHECK: .cfi_def_cfa w29, 16
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; CHECK: .cfi_offset w30, -8
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; CHECK: .cfi_offset w29, -16
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; CHECK: mov x0, sp
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; CHECK: bl _bar
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; [...]
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; CHECK: ldp x29, x30, [sp, #48]
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; CHECK: and x29, x29, #0xefffffffffffffff
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; CHECK: add sp, sp, #64
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%var = alloca i32, i32 10
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call void @bar(i32* %var)
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ret void
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}
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define swifttailcc void @use_input_context(i8* swiftasync %ctx, i8** %ptr) "frame-pointer"="all" {
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; CHECK-LABEL: use_input_context:
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; CHECK-NOAUTH: str x22, [sp
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; CHECK-AUTH: mov x17, x22
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; CHECK-NOT: x22
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; CHECK: str x22, [x0]
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store i8* %ctx, i8** %ptr
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ret void
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}
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define swifttailcc i8** @context_in_func() "frame-pointer"="non-leaf" {
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; CHECK-LABEL: context_in_func:
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; CHECK-NOAUTH: str xzr, [sp, #8]
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; CHECK-AUTH: add x16, sp, #8
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; CHECK-AUTH: movk x16, #49946, lsl #48
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; CHECK-AUTH: mov x17, xzr
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; CHECK-AUTH: pacdb x17, x16
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; CHECK-AUTH: str x17, [sp, #8]
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%ptr = call i8** @llvm.swift.async.context.addr()
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ret i8** %ptr
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}
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define swifttailcc void @write_frame_context(i8* swiftasync %ctx, i8* %newctx) "frame-pointer"="non-leaf" {
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; CHECK-LABEL: write_frame_context:
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; CHECK: sub x[[ADDR:[0-9]+]], x29, #8
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; CHECK: str x0, [x[[ADDR]]]
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%ptr = call i8** @llvm.swift.async.context.addr()
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store i8* %newctx, i8** %ptr
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ret void
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}
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define swifttailcc void @simple_fp_elim(i8* swiftasync %ctx) "frame-pointer"="non-leaf" {
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; CHECK-LABEL: simple_fp_elim:
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; CHECK-NOT: orr x29, x29, #0x100000000000000
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ret void
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}
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define swifttailcc void @large_frame(i8* swiftasync %ctx) "frame-pointer"="all" {
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; CHECK-LABEL: large_frame:
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; CHECK: str x28, [sp, #-32]!
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; CHECK: stp x29, x30, [sp, #16]
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; CHECK-NOAUTH: str x22, [sp, #8]
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; CHECK: add x29, sp, #16
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; CHECK: sub sp, sp, #1024
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; [...]
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; CHECK: add sp, sp, #1024
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; CHECK: ldp x29, x30, [sp, #16]
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; CHECK: ldr x28, [sp], #32
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; CHECK: ret
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%var = alloca i8, i32 1024
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ret void
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}
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; Important point is that there is just one 8-byte gap in the CSR region (right
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; now just above d8) to realign the stack.
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define swifttailcc void @two_unpaired_csrs(i8* swiftasync) "frame-pointer"="all" {
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; CHECK-LABEL: two_unpaired_csrs:
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; CHECK: str d8, [sp, #-48]!
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; CHECK: str x19, [sp, #16]
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; CHECK: stp x29, x30, [sp, #32]
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; CHECK-NOAUTH: str x22, [sp, #24]
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; CHECK: add x29, sp, #32
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; CHECK: .cfi_def_cfa w29, 16
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; CHECK: .cfi_offset w30, -8
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; CHECK: .cfi_offset w29, -16
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; CHECK: .cfi_offset w19, -32
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; CHECK: .cfi_offset b8, -48
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call void asm "","~{x19},~{d8}"()
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call swifttailcc void @bar(i32* undef)
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ret void
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}
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declare swifttailcc void @bar(i32*)
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declare i8** @llvm.swift.async.context.addr()
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