forked from OSchip/llvm-project
237 lines
12 KiB
LLVM
237 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -aarch64-enable-mgather-combine=0 < %s | FileCheck %s
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; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -aarch64-enable-mgather-combine=1 < %s | FileCheck %s
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; Test for multiple uses of the mgather where the s/zext should not be combined
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define <vscale x 2 x i64> @masked_sgather_sext(i8* %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i1> %mask, <vscale x 2 x i8> %vals) {
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; CHECK-LABEL: masked_sgather_sext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, z0.d]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: sxtb z2.d, p0/m, z0.d
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; CHECK-NEXT: add z0.d, z0.d, z1.d
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; CHECK-NEXT: sxtb z0.d, p0/m, z0.d
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; CHECK-NEXT: mul z0.d, p0/m, z0.d, z2.d
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; CHECK-NEXT: ret
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%ptrs = getelementptr i8, i8* %base, <vscale x 2 x i64> %offsets
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%data = call <vscale x 2 x i8> @llvm.masked.gather.nxv2i8(<vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i8> undef)
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%data.sext = sext <vscale x 2 x i8> %data to <vscale x 2 x i64>
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%add = add <vscale x 2 x i8> %data, %vals
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%add.sext = sext <vscale x 2 x i8> %add to <vscale x 2 x i64>
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%mul = mul <vscale x 2 x i64> %data.sext, %add.sext
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ret <vscale x 2 x i64> %mul
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}
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define <vscale x 2 x i64> @masked_sgather_zext(i8* %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i1> %mask, <vscale x 2 x i8> %vals) {
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; CHECK-LABEL: masked_sgather_zext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, z0.d]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: add z1.d, z0.d, z1.d
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; CHECK-NEXT: and z0.d, z0.d, #0xff
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; CHECK-NEXT: and z1.d, z1.d, #0xff
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; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: ret
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%ptrs = getelementptr i8, i8* %base, <vscale x 2 x i64> %offsets
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%data = call <vscale x 2 x i8> @llvm.masked.gather.nxv2i8(<vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i8> undef)
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%data.zext = zext <vscale x 2 x i8> %data to <vscale x 2 x i64>
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%add = add <vscale x 2 x i8> %data, %vals
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%add.zext = zext <vscale x 2 x i8> %add to <vscale x 2 x i64>
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%mul = mul <vscale x 2 x i64> %data.zext, %add.zext
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ret <vscale x 2 x i64> %mul
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}
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; Tests that exercise various type legalisation scenarios for ISD::MGATHER.
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; Code generate load of an illegal datatype via promotion.
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define <vscale x 2 x i8> @masked_gather_nxv2i8(<vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_gather_nxv2i8:
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; CHECK: ld1sb { z0.d }, p0/z, [z0.d]
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; CHECK: ret
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%data = call <vscale x 2 x i8> @llvm.masked.gather.nxv2i8(<vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i8> undef)
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ret <vscale x 2 x i8> %data
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}
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; Code generate load of an illegal datatype via promotion.
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define <vscale x 2 x i16> @masked_gather_nxv2i16(<vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_gather_nxv2i16:
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; CHECK: ld1sh { z0.d }, p0/z, [z0.d]
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; CHECK: ret
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%data = call <vscale x 2 x i16> @llvm.masked.gather.nxv2i16(<vscale x 2 x i16*> %ptrs, i32 2, <vscale x 2 x i1> %mask, <vscale x 2 x i16> undef)
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ret <vscale x 2 x i16> %data
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}
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; Code generate load of an illegal datatype via promotion.
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define <vscale x 2 x i32> @masked_gather_nxv2i32(<vscale x 2 x i32*> %ptrs, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_gather_nxv2i32:
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; CHECK: ld1sw { z0.d }, p0/z, [z0.d]
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; CHECK: ret
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%data = call <vscale x 2 x i32> @llvm.masked.gather.nxv2i32(<vscale x 2 x i32*> %ptrs, i32 4, <vscale x 2 x i1> %mask, <vscale x 2 x i32> undef)
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ret <vscale x 2 x i32> %data
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}
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define <vscale x 4 x half> @masked_gather_nxv4f16(<vscale x 4 x half*> %ptrs, <vscale x 4 x i1> %mask) {
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; CHECK-LABEL: masked_gather_nxv4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: pfalse p1.b
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; CHECK-NEXT: zip2 p2.s, p0.s, p1.s
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; CHECK-NEXT: zip1 p0.s, p0.s, p1.s
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; CHECK-NEXT: ld1h { z1.d }, p2/z, [z1.d]
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; CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d]
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; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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%data = call <vscale x 4 x half> @llvm.masked.gather.nxv4f16(<vscale x 4 x half*> %ptrs, i32 0, <vscale x 4 x i1> %mask, <vscale x 4 x half> undef)
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ret <vscale x 4 x half> %data
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}
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define <vscale x 2 x float> @masked_gather_nxv2f32(float* %base, <vscale x 2 x i16> %indices, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_gather_nxv2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: sxth z0.d, p1/m, z0.d
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; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
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; CHECK-NEXT: ret
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%ptrs = getelementptr float, float* %base, <vscale x 2 x i16> %indices
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%data = call <vscale x 2 x float> @llvm.masked.gather.nxv2f32(<vscale x 2 x float*> %ptrs, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x float> undef)
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ret <vscale x 2 x float> %data
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}
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define <vscale x 8 x half> @masked_gather_nxv8f16(<vscale x 8 x half*> %ptrs, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: masked_gather_nxv8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: pfalse p1.b
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; CHECK-NEXT: zip2 p2.h, p0.h, p1.h
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; CHECK-NEXT: zip1 p0.h, p0.h, p1.h
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; CHECK-NEXT: zip2 p3.s, p2.s, p1.s
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; CHECK-NEXT: zip1 p2.s, p2.s, p1.s
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; CHECK-NEXT: ld1h { z3.d }, p3/z, [z3.d]
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; CHECK-NEXT: ld1h { z2.d }, p2/z, [z2.d]
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; CHECK-NEXT: zip2 p2.s, p0.s, p1.s
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; CHECK-NEXT: zip1 p0.s, p0.s, p1.s
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; CHECK-NEXT: ld1h { z1.d }, p2/z, [z1.d]
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; CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d]
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; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s
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; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
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; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
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; CHECK-NEXT: ret
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%data = call <vscale x 8 x half> @llvm.masked.gather.nxv8f16(<vscale x 8 x half*> %ptrs, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x half> undef)
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ret <vscale x 8 x half> %data
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}
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define <vscale x 8 x bfloat> @masked_gather_nxv8bf16(bfloat* %base, <vscale x 8 x i16> %indices, <vscale x 8 x i1> %mask) #0 {
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; CHECK-LABEL: masked_gather_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: pfalse p1.b
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; CHECK-NEXT: sunpkhi z1.s, z0.h
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; CHECK-NEXT: sunpklo z0.s, z0.h
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; CHECK-NEXT: zip2 p2.h, p0.h, p1.h
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; CHECK-NEXT: zip1 p0.h, p0.h, p1.h
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; CHECK-NEXT: ld1h { z1.s }, p2/z, [x0, z1.s, sxtw #1]
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; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, z0.s, sxtw #1]
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; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%ptrs = getelementptr bfloat, bfloat* %base, <vscale x 8 x i16> %indices
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%data = call <vscale x 8 x bfloat> @llvm.masked.gather.nxv8bf16(<vscale x 8 x bfloat*> %ptrs, i32 1, <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> undef)
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ret <vscale x 8 x bfloat> %data
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}
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define <vscale x 4 x double> @masked_gather_nxv4f64(double* %base, <vscale x 4 x i16> %indices, <vscale x 4 x i1> %mask) {;
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; CHECK-LABEL: masked_gather_nxv4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: pfalse p2.b
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; CHECK-NEXT: sxth z0.s, p1/m, z0.s
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; CHECK-NEXT: zip1 p1.s, p0.s, p2.s
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; CHECK-NEXT: zip2 p0.s, p0.s, p2.s
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; CHECK-NEXT: sunpklo z1.d, z0.s
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; CHECK-NEXT: sunpkhi z2.d, z0.s
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; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0, z1.d, lsl #3]
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; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, z2.d, lsl #3]
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; CHECK-NEXT: ret
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%ptrs = getelementptr double, double* %base, <vscale x 4 x i16> %indices
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%data = call <vscale x 4 x double> @llvm.masked.gather.nxv4f64(<vscale x 4 x double*> %ptrs, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x double> undef)
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ret <vscale x 4 x double> %data
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}
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define <vscale x 8 x float> @masked_gather_nxv8f32(float* %base, <vscale x 8 x i32> %offsets, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: masked_gather_nxv8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: pfalse p1.b
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; CHECK-NEXT: zip1 p2.h, p0.h, p1.h
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; CHECK-NEXT: zip2 p0.h, p0.h, p1.h
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; CHECK-NEXT: ld1w { z0.s }, p2/z, [x0, z0.s, uxtw #2]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0, z1.s, uxtw #2]
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; CHECK-NEXT: ret
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%offsets.zext = zext <vscale x 8 x i32> %offsets to <vscale x 8 x i64>
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%ptrs = getelementptr float, float* %base, <vscale x 8 x i64> %offsets.zext
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%vals = call <vscale x 8 x float> @llvm.masked.gather.nxv8f32(<vscale x 8 x float*> %ptrs, i32 4, <vscale x 8 x i1> %mask, <vscale x 8 x float> undef)
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ret <vscale x 8 x float> %vals
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}
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; Code generate the worst case scenario when all vector types are legal.
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define <vscale x 16 x i8> @masked_gather_nxv16i8(i8* %base, <vscale x 16 x i8> %indices, <vscale x 16 x i1> %mask) {
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; CHECK-LABEL: masked_gather_nxv16i8:
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; CHECK-DAG: ld1sb { {{z[0-9]+}}.s }, {{p[0-9]+}}/z, [x0, {{z[0-9]+}}.s, sxtw]
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; CHECK-DAG: ld1sb { {{z[0-9]+}}.s }, {{p[0-9]+}}/z, [x0, {{z[0-9]+}}.s, sxtw]
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; CHECK-DAG: ld1sb { {{z[0-9]+}}.s }, {{p[0-9]+}}/z, [x0, {{z[0-9]+}}.s, sxtw]
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; CHECK-DAG: ld1sb { {{z[0-9]+}}.s }, {{p[0-9]+}}/z, [x0, {{z[0-9]+}}.s, sxtw]
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; CHECK: ret
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%ptrs = getelementptr i8, i8* %base, <vscale x 16 x i8> %indices
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%data = call <vscale x 16 x i8> @llvm.masked.gather.nxv16i8(<vscale x 16 x i8*> %ptrs, i32 1, <vscale x 16 x i1> %mask, <vscale x 16 x i8> undef)
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ret <vscale x 16 x i8> %data
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}
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; Code generate the worst case scenario when all vector types are illegal.
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define <vscale x 32 x i32> @masked_gather_nxv32i32(i32* %base, <vscale x 32 x i32> %indices, <vscale x 32 x i1> %mask) {
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; CHECK-LABEL: masked_gather_nxv32i32:
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; CHECK-NOT: unpkhi
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; CHECK-DAG: ld1w { {{z[0-9]+}}.s }, {{p[0-9]+}}/z, [x0, z0.s, sxtw #2]
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; CHECK-DAG: ld1w { {{z[0-9]+}}.s }, {{p[0-9]+}}/z, [x0, z1.s, sxtw #2]
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; CHECK-DAG: ld1w { {{z[0-9]+}}.s }, {{p[0-9]+}}/z, [x0, z2.s, sxtw #2]
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; CHECK-DAG: ld1w { {{z[0-9]+}}.s }, {{p[0-9]+}}/z, [x0, z3.s, sxtw #2]
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; CHECK-DAG: ld1w { {{z[0-9]+}}.s }, {{p[0-9]+}}/z, [x0, z4.s, sxtw #2]
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; CHECK-DAG: ld1w { {{z[0-9]+}}.s }, {{p[0-9]+}}/z, [x0, z5.s, sxtw #2]
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; CHECK-DAG: ld1w { {{z[0-9]+}}.s }, {{p[0-9]+}}/z, [x0, z6.s, sxtw #2]
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; CHECK-DAG: ld1w { {{z[0-9]+}}.s }, {{p[0-9]+}}/z, [x0, z7.s, sxtw #2]
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; CHECK: ret
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%ptrs = getelementptr i32, i32* %base, <vscale x 32 x i32> %indices
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%data = call <vscale x 32 x i32> @llvm.masked.gather.nxv32i32(<vscale x 32 x i32*> %ptrs, i32 4, <vscale x 32 x i1> %mask, <vscale x 32 x i32> undef)
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ret <vscale x 32 x i32> %data
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}
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; TODO: Currently, the sign extend gets applied to the values after a 'uzp1' of two
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; registers, so it doesn't get folded away. Same for any other vector-of-pointers
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; style gathers which don't fit in an <vscale x 2 x type*> single register. Better folding
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; is required before we can check those off.
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define <vscale x 4 x i32> @masked_sgather_nxv4i8(<vscale x 4 x i8*> %ptrs, <vscale x 4 x i1> %mask) {
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; CHECK-LABEL: masked_sgather_nxv4i8:
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; CHECK: pfalse p1.b
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; CHECK-NEXT: zip2 p2.s, p0.s, p1.s
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; CHECK-NEXT: zip1 p0.s, p0.s, p1.s
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; CHECK-NEXT: ld1sb { z1.d }, p2/z, [z1.d]
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; CHECK-NEXT: ld1sb { z0.d }, p0/z, [z0.d]
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
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; CHECK-NEXT: sxtb z0.s, p0/m, z0.s
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; CHECK-NEXT: ret
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%vals = call <vscale x 4 x i8> @llvm.masked.gather.nxv4i8(<vscale x 4 x i8*> %ptrs, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i8> undef)
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%svals = sext <vscale x 4 x i8> %vals to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %svals
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}
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declare <vscale x 2 x i8> @llvm.masked.gather.nxv2i8(<vscale x 2 x i8*>, i32, <vscale x 2 x i1>, <vscale x 2 x i8>)
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declare <vscale x 2 x i16> @llvm.masked.gather.nxv2i16(<vscale x 2 x i16*>, i32, <vscale x 2 x i1>, <vscale x 2 x i16>)
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declare <vscale x 2 x i32> @llvm.masked.gather.nxv2i32(<vscale x 2 x i32*>, i32, <vscale x 2 x i1>, <vscale x 2 x i32>)
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declare <vscale x 4 x i8> @llvm.masked.gather.nxv4i8(<vscale x 4 x i8*>, i32, <vscale x 4 x i1>, <vscale x 4 x i8>)
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declare <vscale x 16 x i8> @llvm.masked.gather.nxv16i8(<vscale x 16 x i8*>, i32, <vscale x 16 x i1>, <vscale x 16 x i8>)
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declare <vscale x 32 x i32> @llvm.masked.gather.nxv32i32(<vscale x 32 x i32*>, i32, <vscale x 32 x i1>, <vscale x 32 x i32>)
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declare <vscale x 4 x half> @llvm.masked.gather.nxv4f16(<vscale x 4 x half*>, i32, <vscale x 4 x i1>, <vscale x 4 x half>)
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declare <vscale x 8 x half> @llvm.masked.gather.nxv8f16(<vscale x 8 x half*>, i32, <vscale x 8 x i1>, <vscale x 8 x half>)
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declare <vscale x 8 x bfloat> @llvm.masked.gather.nxv8bf16(<vscale x 8 x bfloat*>, i32, <vscale x 8 x i1>, <vscale x 8 x bfloat>)
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declare <vscale x 2 x float> @llvm.masked.gather.nxv2f32(<vscale x 2 x float*>, i32, <vscale x 2 x i1>, <vscale x 2 x float>)
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declare <vscale x 8 x float> @llvm.masked.gather.nxv8f32(<vscale x 8 x float*>, i32, <vscale x 8 x i1>, <vscale x 8 x float>)
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declare <vscale x 4 x double> @llvm.masked.gather.nxv4f64(<vscale x 4 x double*>, i32, <vscale x 4 x i1>, <vscale x 4 x double>)
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attributes #0 = { "target-features"="+sve,+bf16" }
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