forked from OSchip/llvm-project
263 lines
8.7 KiB
LLVM
263 lines
8.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; INDEX (IMMEDIATES)
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;
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define <vscale x 16 x i8> @index_ii_i8() {
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; CHECK-LABEL: index_ii_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.b, #-16, #15
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 -16, i8 15)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @index_ii_i16() {
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; CHECK-LABEL: index_ii_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.h, #15, #-16
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 15, i16 -16)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @index_ii_i32() {
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; CHECK-LABEL: index_ii_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.s, #-16, #15
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 -16, i32 15)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @index_ii_i64() {
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; CHECK-LABEL: index_ii_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.d, #15, #-16
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 15, i64 -16)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 2 x i64> @index_ii_range() {
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; CHECK-LABEL: index_ii_range:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #16
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; CHECK-NEXT: mov x9, #-17
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; CHECK-NEXT: index z0.d, x9, x8
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 -17, i64 16)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 8 x i16> @index_ii_range_combine(i16 %a) {
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; CHECK-LABEL: index_ii_range_combine:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.h, #2, #8
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; CHECK-NEXT: ret
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%val = insertelement <vscale x 8 x i16> poison, i16 2, i32 0
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%val1 = shufflevector <vscale x 8 x i16> %val, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
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%val2 = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 0, i16 2)
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%val3 = shl <vscale x 8 x i16> %val2, %val1
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%out = add <vscale x 8 x i16> %val3, %val1
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ret <vscale x 8 x i16> %out
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}
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;
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; INDEX (IMMEDIATE, SCALAR)
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;
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define <vscale x 16 x i8> @index_ir_i8(i8 %a) {
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; CHECK-LABEL: index_ir_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.b, #15, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 15, i8 %a)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @index_ir_i16(i16 %a) {
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; CHECK-LABEL: index_ir_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.h, #-16, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 -16, i16 %a)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @index_ir_i32(i32 %a) {
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; CHECK-LABEL: index_ir_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.s, #15, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 15, i32 %a)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @index_ir_i64(i64 %a) {
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; CHECK-LABEL: index_ir_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.d, #-16, x0
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 -16, i64 %a)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 4 x i32> @index_ir_range(i32 %a) {
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; CHECK-LABEL: index_ir_range:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-17
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; CHECK-NEXT: index z0.s, w8, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 -17, i32 %a)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 4 x i32> @index_ir_range_combine(i32 %a) {
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; CHECK-LABEL: index_ir_range_combine:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.s, #0, w0
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; CHECK-NEXT: ret
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%val = insertelement <vscale x 4 x i32> poison, i32 2, i32 0
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%val1 = shufflevector <vscale x 4 x i32> %val, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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%tmp = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 2, i32 1)
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%tmp1 = sub <vscale x 4 x i32> %tmp, %val1
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%val2 = insertelement <vscale x 4 x i32> poison, i32 %a, i32 0
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%val3 = shufflevector <vscale x 4 x i32> %val2, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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%out = mul <vscale x 4 x i32> %tmp1, %val3
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ret <vscale x 4 x i32> %out
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}
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;
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; INDEX (SCALAR, IMMEDIATE)
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;
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define <vscale x 16 x i8> @index_ri_i8(i8 %a) {
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; CHECK-LABEL: index_ri_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.b, w0, #-16
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %a, i8 -16)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @index_ri_i16(i16 %a) {
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; CHECK-LABEL: index_ri_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.h, w0, #15
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %a, i16 15)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @index_ri_i32(i32 %a) {
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; CHECK-LABEL: index_ri_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.s, w0, #-16
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %a, i32 -16)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @index_ri_i64(i64 %a) {
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; CHECK-LABEL: index_ri_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.d, x0, #15
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %a, i64 15)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 8 x i16> @index_ri_range(i16 %a) {
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; CHECK-LABEL: index_ri_range:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #16
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; CHECK-NEXT: index z0.h, w0, w8
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %a, i16 16)
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ret <vscale x 8 x i16> %out
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}
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;
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; INDEX (SCALARS)
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;
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define <vscale x 16 x i8> @index_rr_i8(i8 %a, i8 %b) {
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; CHECK-LABEL: index_rr_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.b, w0, w1
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %a, i8 %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @index_rr_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: index_rr_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.h, w0, w1
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %a, i16 %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @index_rr_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: index_rr_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.s, w0, w1
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %a, i32 %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @index_rr_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: index_rr_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.d, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %a, i64 %b)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 4 x i32> @index_rr_i32_combine(i32 %a, i32 %b) {
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; CHECK-LABEL: index_rr_i32_combine:
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; CHECK: // %bb.0:
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; CHECK-NEXT: index z0.s, w0, w1
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; CHECK-NEXT: ret
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%val = insertelement <vscale x 4 x i32> poison, i32 %a, i32 0
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%val1 = shufflevector <vscale x 4 x i32> %val, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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%val2 = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
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%val3 = shufflevector <vscale x 4 x i32> %val2, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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%tmp = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 0, i32 1)
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%tmp1 = mul <vscale x 4 x i32> %tmp, %val3
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%out = add <vscale x 4 x i32> %tmp1, %val1
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 4 x i32> @index_rr_i32_not_combine(i32 %a, i32 %b) {
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; CHECK-LABEL: index_rr_i32_not_combine:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z0.s, w0
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; CHECK-NEXT: mov z1.s, w1
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; CHECK-NEXT: index z2.s, #0, #1
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: mla z0.s, p0/m, z2.s, z1.s
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; CHECK-NEXT: add z0.s, z0.s, z2.s
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; CHECK-NEXT: ret
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%val = insertelement <vscale x 4 x i32> poison, i32 %a, i32 0
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%val1 = shufflevector <vscale x 4 x i32> %val, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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%val2 = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
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%val3 = shufflevector <vscale x 4 x i32> %val2, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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%tmp = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 0, i32 1)
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%tmp1 = mul <vscale x 4 x i32> %tmp, %val3
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%tmp2 = add <vscale x 4 x i32> %tmp1, %val1
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%out = add <vscale x 4 x i32> %tmp2, %tmp
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ret <vscale x 4 x i32> %out
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8, i8)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16, i16)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32, i32)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64, i64)
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