forked from OSchip/llvm-project
366 lines
16 KiB
LLVM
366 lines
16 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK
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define <vscale x 2 x i64> @insert_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {
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; CHECK-LABEL: insert_v2i64_nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z0.d }, p0, [sp]
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; CHECK-NEXT: str q1, [sp]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 0)
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ret <vscale x 2 x i64> %retval
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}
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define <vscale x 2 x i64> @insert_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {
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; CHECK-LABEL: insert_v2i64_nxv2i64_idx2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: cntd x9
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; CHECK-NEXT: sub x9, x9, #2 // =2
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; CHECK-NEXT: mov w8, #2
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; CHECK-NEXT: cmp x9, #2 // =2
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; CHECK-NEXT: csel x8, x9, x8, lo
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: lsl x8, x8, #3
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: st1d { z0.d }, p0, [sp]
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; CHECK-NEXT: str q1, [x9, x8]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2)
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ret <vscale x 2 x i64> %retval
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}
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define <vscale x 4 x i32> @insert_v4i32_nxv4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {
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; CHECK-LABEL: insert_v4i32_nxv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: st1w { z0.s }, p0, [sp]
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; CHECK-NEXT: str q1, [sp]
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0)
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ret <vscale x 4 x i32> %retval
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}
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define <vscale x 4 x i32> @insert_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {
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; CHECK-LABEL: insert_v4i32_nxv4i32_idx4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: cntw x9
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; CHECK-NEXT: sub x9, x9, #4 // =4
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; CHECK-NEXT: mov w8, #4
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; CHECK-NEXT: cmp x9, #4 // =4
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; CHECK-NEXT: csel x8, x9, x8, lo
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: lsl x8, x8, #2
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: st1w { z0.s }, p0, [sp]
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; CHECK-NEXT: str q1, [x9, x8]
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 4)
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ret <vscale x 4 x i32> %retval
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}
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define <vscale x 8 x i16> @insert_v8i16_nxv8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {
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; CHECK-LABEL: insert_v8i16_nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: st1h { z0.h }, p0, [sp]
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; CHECK-NEXT: str q1, [sp]
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 0)
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ret <vscale x 8 x i16> %retval
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}
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define <vscale x 8 x i16> @insert_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {
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; CHECK-LABEL: insert_v8i16_nxv8i16_idx8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: cnth x9
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; CHECK-NEXT: sub x9, x9, #8 // =8
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; CHECK-NEXT: mov w8, #8
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; CHECK-NEXT: cmp x9, #8 // =8
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; CHECK-NEXT: csel x8, x9, x8, lo
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: lsl x8, x8, #1
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: st1h { z0.h }, p0, [sp]
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; CHECK-NEXT: str q1, [x9, x8]
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 8)
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ret <vscale x 8 x i16> %retval
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}
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define <vscale x 16 x i8> @insert_v16i8_nxv16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {
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; CHECK-LABEL: insert_v16i8_nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: st1b { z0.b }, p0, [sp]
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; CHECK-NEXT: str q1, [sp]
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 0)
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ret <vscale x 16 x i8> %retval
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}
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define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {
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; CHECK-LABEL: insert_v16i8_nxv16i8_idx16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: rdvl x9, #1
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; CHECK-NEXT: sub x9, x9, #16 // =16
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; CHECK-NEXT: mov w8, #16
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; CHECK-NEXT: cmp x9, #16 // =16
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: csel x8, x9, x8, lo
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: st1b { z0.b }, p0, [sp]
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; CHECK-NEXT: str q1, [x9, x8]
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 16)
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ret <vscale x 16 x i8> %retval
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}
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; Insert subvectors into illegal vectors
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define void @insert_nxv8i64_nxv16i64(<vscale x 8 x i64> %sv0, <vscale x 8 x i64> %sv1, <vscale x 16 x i64>* %out) {
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; CHECK-LABEL: insert_nxv8i64_nxv16i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z7.d }, p0, [x0, #7, mul vl]
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; CHECK-NEXT: st1d { z6.d }, p0, [x0, #6, mul vl]
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; CHECK-NEXT: st1d { z5.d }, p0, [x0, #5, mul vl]
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; CHECK-NEXT: st1d { z4.d }, p0, [x0, #4, mul vl]
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; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl]
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; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: st1d { z0.d }, p0, [x0]
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; CHECK-NEXT: ret
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%v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0)
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%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %v0, <vscale x 8 x i64> %sv1, i64 8)
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store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
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ret void
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}
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define void @insert_nxv8i64_nxv16i64_lo(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) {
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; CHECK-LABEL: insert_nxv8i64_nxv16i64_lo:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl]
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; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: st1d { z0.d }, p0, [x0]
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0)
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store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
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ret void
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}
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define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) {
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; CHECK-LABEL: insert_nxv8i64_nxv16i64_hi:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z3.d }, p0, [x0, #7, mul vl]
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; CHECK-NEXT: st1d { z2.d }, p0, [x0, #6, mul vl]
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; CHECK-NEXT: st1d { z1.d }, p0, [x0, #5, mul vl]
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; CHECK-NEXT: st1d { z0.d }, p0, [x0, #4, mul vl]
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 8)
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store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
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ret void
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}
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define void @insert_v2i64_nxv16i64(<2 x i64> %sv0, <2 x i64> %sv1, <vscale x 16 x i64>* %out) {
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; CHECK-LABEL: insert_v2i64_nxv16i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-4
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: mov x8, sp
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; CHECK-NEXT: st1d { z0.d }, p0, [sp]
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; CHECK-NEXT: str q1, [sp, #32]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #1, mul vl]
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; CHECK-NEXT: ld1d { z1.d }, p0/z, [x8, #2, mul vl]
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; CHECK-NEXT: ld1d { z2.d }, p0/z, [x8, #3, mul vl]
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; CHECK-NEXT: ld1d { z3.d }, p0/z, [sp]
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; CHECK-NEXT: st1d { z2.d }, p0, [x0, #3, mul vl]
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; CHECK-NEXT: st1d { z1.d }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: st1d { z3.d }, p0, [x0]
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; CHECK-NEXT: addvl sp, sp, #4
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0)
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%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4)
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store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
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ret void
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}
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define void @insert_v2i64_nxv16i64_lo0(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
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; CHECK-LABEL: insert_v2i64_nxv16i64_lo0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%sv = load <2 x i64>, <2 x i64>* %psv
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%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 0)
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store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
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ret void
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}
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define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
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; CHECK-LABEL: insert_v2i64_nxv16i64_lo2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-2
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: mov x8, sp
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; CHECK-NEXT: str q0, [sp, #16]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #1, mul vl]
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; CHECK-NEXT: ld1d { z1.d }, p0/z, [sp]
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; CHECK-NEXT: st1d { z0.d }, p0, [x1, #1, mul vl]
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; CHECK-NEXT: st1d { z1.d }, p0, [x1]
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; CHECK-NEXT: addvl sp, sp, #2
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%sv = load <2 x i64>, <2 x i64>* %psv
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%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2)
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store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
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ret void
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}
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; Insert subvectors that need widening
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define <vscale x 4 x i32> @insert_nxv1i32_nxv4i32_undef() nounwind {
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; CHECK-LABEL: insert_nxv1i32_nxv4i32_undef:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.s, #1 // =0x1
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; CHECK-NEXT: ret
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entry:
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%0 = insertelement <vscale x 1 x i32> undef, i32 1, i32 0
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%subvec = shufflevector <vscale x 1 x i32> %0, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
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%retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> %subvec, i64 0)
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ret <vscale x 4 x i32> %retval
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}
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define <vscale x 6 x i16> @insert_nxv1i16_nxv6i16_undef() nounwind {
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; CHECK-LABEL: insert_nxv1i16_nxv6i16_undef:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.h, #1 // =0x1
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; CHECK-NEXT: ret
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entry:
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%0 = insertelement <vscale x 1 x i16> undef, i16 1, i32 0
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%subvec = shufflevector <vscale x 1 x i16> %0, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
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%retval = call <vscale x 6 x i16> @llvm.experimental.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16> undef, <vscale x 1 x i16> %subvec, i64 0)
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ret <vscale x 6 x i16> %retval
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}
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; Fixed length clamping
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define <vscale x 2 x i64> @insert_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind #0 {
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; CHECK-LABEL: insert_fixed_v2i64_nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: cntd x9
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; CHECK-NEXT: sub x9, x9, #2 // =2
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; CHECK-NEXT: mov w8, #2
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; CHECK-NEXT: cmp x9, #2 // =2
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; CHECK-NEXT: csel x8, x9, x8, lo
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: lsl x8, x8, #3
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: st1d { z0.d }, p0, [sp]
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; CHECK-NEXT: str q1, [x9, x8]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2)
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ret <vscale x 2 x i64> %retval
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}
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define <vscale x 2 x i64> @insert_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec, <4 x i64>* %ptr) nounwind #0 {
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; CHECK-LABEL: insert_fixed_v4i64_nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.d, vl4
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; CHECK-NEXT: cntd x8
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; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]
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; CHECK-NEXT: subs x8, x8, #4 // =4
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; CHECK-NEXT: csel x8, xzr, x8, lo
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; CHECK-NEXT: mov w9, #4
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; CHECK-NEXT: cmp x8, #4 // =4
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: csel x8, x8, x9, lo
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: st1d { z0.d }, p1, [sp]
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; CHECK-NEXT: st1d { z1.d }, p0, [x9, x8, lsl #3]
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; CHECK-NEXT: ld1d { z0.d }, p1/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%subvec = load <4 x i64>, <4 x i64>* %ptr
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%retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> %vec, <4 x i64> %subvec, i64 4)
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ret <vscale x 2 x i64> %retval
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}
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attributes #0 = { vscale_range(2,2) }
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declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64)
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declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64)
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declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64)
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declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64)
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declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64>, <4 x i64>, i64)
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declare <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64)
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declare <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64)
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declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32>, <vscale x 1 x i32>, i64)
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declare <vscale x 6 x i16> @llvm.experimental.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16>, <vscale x 1 x i16>, i64)
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