forked from OSchip/llvm-project
225 lines
8.7 KiB
LLVM
225 lines
8.7 KiB
LLVM
; RUN: llc -aarch64-sve-vector-bits-min=128 -asm-verbose=0 < %s | FileCheck %s -check-prefix=NO_SVE
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; RUN: llc -aarch64-sve-vector-bits-min=256 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
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; RUN: llc -aarch64-sve-vector-bits-min=384 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
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; RUN: llc -aarch64-sve-vector-bits-min=512 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=640 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=768 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=896 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=1024 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1152 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1280 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1408 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1536 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1664 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1792 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1920 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=2048 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024,VBITS_GE_2048
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target triple = "aarch64-unknown-linux-gnu"
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; Don't use SVE when its registers are no bigger than NEON.
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; NO_SVE-NOT: ptrue
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;
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; extractelement
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;
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; Don't use SVE for 64-bit vectors.
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define half @extractelement_v4f16(<4 x half> %op1) #0 {
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; CHECK-LABEL: extractelement_v4f16:
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; CHECK: mov h0, v0.h[3]
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; CHECK-NEXT: ret
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%r = extractelement <4 x half> %op1, i64 3
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ret half %r
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}
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; Don't use SVE for 128-bit vectors.
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define half @extractelement_v8f16(<8 x half> %op1) #0 {
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; CHECK-LABEL: extractelement_v8f16:
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; CHECK: mov h0, v0.h[7]
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; CHECK-NEXT: ret
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%r = extractelement <8 x half> %op1, i64 7
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ret half %r
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}
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define half @extractelement_v16f16(<16 x half>* %a) #0 {
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; CHECK-LABEL: extractelement_v16f16:
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; VBITS_GE_256: ptrue p0.h, vl16
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; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0]
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; VBITS_GE_256-NEXT: mov z0.h, z0.h[15]
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; VBITS_GE_256-NEXT: ret
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%op1 = load <16 x half>, <16 x half>* %a
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%r = extractelement <16 x half> %op1, i64 15
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ret half %r
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}
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define half @extractelement_v32f16(<32 x half>* %a) #0 {
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; CHECK-LABEL: extractelement_v32f16:
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; VBITS_GE_512: ptrue p0.h, vl32
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; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
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; VBITS_GE_512-NEXT: mov z0.h, z0.h[31]
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; VBITS_GE_512-NEXT: ret
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%op1 = load <32 x half>, <32 x half>* %a
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%r = extractelement <32 x half> %op1, i64 31
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ret half %r
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}
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define half @extractelement_v64f16(<64 x half>* %a) #0 {
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; CHECK-LABEL: extractelement_v64f16:
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; VBITS_GE_1024: ptrue p0.h, vl64
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; VBITS_GE_1024-NEXT: ld1h { z0.h }, p0/z, [x0]
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; VBITS_GE_1024-NEXT: mov w8, #63
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; VBITS_GE_1024-NEXT: whilels p0.h, xzr, x8
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; VBITS_GE_1024-NEXT: lastb h0, p0, z0.h
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; VBITS_GE_1024-NEXT: ret
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%op1 = load <64 x half>, <64 x half>* %a
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%r = extractelement <64 x half> %op1, i64 63
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ret half %r
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}
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define half @extractelement_v128f16(<128 x half>* %a) #0 {
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; CHECK-LABEL: extractelement_v128f16:
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; VBITS_GE_2048: ptrue p0.h, vl128
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; VBITS_GE_2048-NEXT: ld1h { z0.h }, p0/z, [x0]
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; VBITS_GE_2048-NEXT: mov w8, #127
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; VBITS_GE_2048-NEXT: whilels p0.h, xzr, x8
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; VBITS_GE_2048-NEXT: lastb h0, p0, z0.h
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; VBITS_GE_2048-NEXT: ret
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%op1 = load <128 x half>, <128 x half>* %a
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%r = extractelement <128 x half> %op1, i64 127
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ret half %r
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}
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; Don't use SVE for 64-bit vectors.
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define float @extractelement_v2f32(<2 x float> %op1) #0 {
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; CHECK-LABEL: extractelement_v2f32:
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; CHECK: mov s0, v0.s[1]
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; CHECK-NEXT: ret
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%r = extractelement <2 x float> %op1, i64 1
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ret float %r
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}
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; Don't use SVE for 128-bit vectors.
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define float @extractelement_v4f32(<4 x float> %op1) #0 {
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; CHECK-LABEL: extractelement_v4f32:
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; CHECK: mov s0, v0.s[3]
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; CHECK-NEXT: ret
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%r = extractelement <4 x float> %op1, i64 3
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ret float %r
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}
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define float @extractelement_v8f32(<8 x float>* %a) #0 {
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; CHECK-LABEL: extractelement_v8f32:
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; VBITS_GE_256: ptrue p0.s, vl8
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; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_256-NEXT: mov z0.s, z0.s[7]
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; VBITS_GE_256-NEXT: ret
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%op1 = load <8 x float>, <8 x float>* %a
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%r = extractelement <8 x float> %op1, i64 7
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ret float %r
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}
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define float @extractelement_v16f32(<16 x float>* %a) #0 {
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; CHECK-LABEL: extractelement_v16f32:
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; VBITS_GE_512: ptrue p0.s, vl16
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; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_512-NEXT: mov z0.s, z0.s[15]
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; VBITS_GE_512-NEXT: ret
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%op1 = load <16 x float>, <16 x float>* %a
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%r = extractelement <16 x float> %op1, i64 15
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ret float %r
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}
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define float @extractelement_v32f32(<32 x float>* %a) #0 {
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; CHECK-LABEL: extractelement_v32f32:
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; VBITS_GE_1024: ptrue p0.s, vl32
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; VBITS_GE_1024-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_1024-NEXT: mov w8, #31
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; VBITS_GE_1024-NEXT: whilels p0.s, xzr, x8
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; VBITS_GE_1024-NEXT: lastb s0, p0, z0.s
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; VBITS_GE_1024-NEXT: ret
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%op1 = load <32 x float>, <32 x float>* %a
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%r = extractelement <32 x float> %op1, i64 31
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ret float %r
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}
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define float @extractelement_v64f32(<64 x float>* %a) #0 {
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; CHECK-LABEL: extractelement_v64f32:
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; VBITS_GE_2048: ptrue p0.s, vl64
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; VBITS_GE_2048-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_2048-NEXT: mov w8, #63
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; VBITS_GE_2048-NEXT: whilels p0.s, xzr, x8
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; VBITS_GE_2048-NEXT: lastb s0, p0, z0.s
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; VBITS_GE_2048-NEXT: ret
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%op1 = load <64 x float>, <64 x float>* %a
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%r = extractelement <64 x float> %op1, i64 63
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ret float %r
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}
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; Don't use SVE for 64-bit vectors.
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define double @extractelement_v1f64(<1 x double> %op1) #0 {
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; CHECK-LABEL: extractelement_v1f64:
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; CHECK: ret
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%r = extractelement <1 x double> %op1, i64 0
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ret double %r
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}
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; Don't use SVE for 128-bit vectors.
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define double @extractelement_v2f64(<2 x double> %op1) #0 {
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; CHECK-LABEL: extractelement_v2f64:
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; CHECK: mov d0, v0.d[1]
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; CHECK-NEXT: ret
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%r = extractelement <2 x double> %op1, i64 1
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ret double %r
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}
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define double @extractelement_v4f64(<4 x double>* %a) #0 {
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; CHECK-LABEL: extractelement_v4f64:
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; VBITS_GE_256: ptrue p0.d, vl4
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; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0]
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; VBITS_GE_256-NEXT: mov z0.d, z0.d[3]
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; VBITS_GE_256-NEXT: ret
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%op1 = load <4 x double>, <4 x double>* %a
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%r = extractelement <4 x double> %op1, i64 3
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ret double %r
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}
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define double @extractelement_v8f64(<8 x double>* %a) #0 {
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; CHECK-LABEL: extractelement_v8f64:
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; VBITS_GE_512: ptrue p0.d, vl8
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; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
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; VBITS_GE_512-NEXT: mov z0.d, z0.d[7]
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; VBITS_GE_512-NEXT: ret
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%op1 = load <8 x double>, <8 x double>* %a
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%r = extractelement <8 x double> %op1, i64 7
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ret double %r
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}
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define double @extractelement_v16f64(<16 x double>* %a) #0 {
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; CHECK-LABEL: extractelement_v16f64:
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; VBITS_GE_1024: ptrue p0.d, vl16
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; VBITS_GE_1024-NEXT: ld1d { z0.d }, p0/z, [x0]
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; VBITS_GE_1024-NEXT: mov w8, #15
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; VBITS_GE_1024-NEXT: whilels p0.d, xzr, x8
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; VBITS_GE_1024-NEXT: lastb d0, p0, z0.d
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; VBITS_GE_1024-NEXT: ret
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%op1 = load <16 x double>, <16 x double>* %a
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%r = extractelement <16 x double> %op1, i64 15
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ret double %r
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}
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define double @extractelement_v32f64(<32 x double>* %a) #0 {
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; CHECK-LABEL: extractelement_v32f64:
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; VBITS_GE_2048: ptrue p0.d, vl32
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; VBITS_GE_2048-NEXT: ld1d { z0.d }, p0/z, [x0]
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; VBITS_GE_2048-NEXT: mov w8, #31
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; VBITS_GE_2048-NEXT: whilels p0.d, xzr, x8
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; VBITS_GE_2048-NEXT: lastb d0, p0, z0.d
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; VBITS_GE_2048-NEXT: ret
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%op1 = load <32 x double>, <32 x double>* %a
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%r = extractelement <32 x double> %op1, i64 31
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ret double %r
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}
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attributes #0 = { "target-features"="+sve" }
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