forked from OSchip/llvm-project
154 lines
4.3 KiB
LLVM
154 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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define i8 @shl_and(i8 %x, i8 %y) nounwind {
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; CHECK-LABEL: shl_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #5
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; CHECK-NEXT: and w0, w8, w1, lsl #2
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; CHECK-NEXT: ret
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%sh0 = shl i8 %x, 3
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%r = and i8 %sh0, %y
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%sh1 = shl i8 %r, 2
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ret i8 %sh1
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}
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define i16 @shl_or(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: shl_or:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #12
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; CHECK-NEXT: orr w0, w8, w1, lsl #7
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; CHECK-NEXT: ret
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%sh0 = shl i16 %x, 5
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%r = or i16 %y, %sh0
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%sh1 = shl i16 %r, 7
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ret i16 %sh1
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}
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define i32 @shl_xor(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: shl_xor:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #12
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; CHECK-NEXT: eor w0, w8, w1, lsl #7
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; CHECK-NEXT: ret
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%sh0 = shl i32 %x, 5
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%r = xor i32 %sh0, %y
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%sh1 = shl i32 %r, 7
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ret i32 %sh1
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}
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define i64 @lshr_and(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: lshr_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, #12
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; CHECK-NEXT: and x0, x8, x1, lsr #7
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; CHECK-NEXT: ret
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%sh0 = lshr i64 %x, 5
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%r = and i64 %y, %sh0
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%sh1 = lshr i64 %r, 7
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ret i64 %sh1
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}
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define <4 x i32> @lshr_or(<4 x i32> %x, <4 x i32> %y) nounwind {
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; CHECK-LABEL: lshr_or:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v1.4s, v1.4s, #7
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; CHECK-NEXT: ushr v0.4s, v0.4s, #12
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%sh0 = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
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%r = or <4 x i32> %sh0, %y
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%sh1 = lshr <4 x i32> %r, <i32 7, i32 7, i32 7, i32 7>
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ret <4 x i32> %sh1
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}
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define <8 x i16> @lshr_xor(<8 x i16> %x, <8 x i16> %y) nounwind {
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; CHECK-LABEL: lshr_xor:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v1.8h, v1.8h, #7
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; CHECK-NEXT: ushr v0.8h, v0.8h, #12
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%sh0 = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%r = xor <8 x i16> %y, %sh0
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%sh1 = lshr <8 x i16> %r, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %sh1
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}
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define <16 x i8> @ashr_and(<16 x i8> %x, <16 x i8> %y) nounwind {
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; CHECK-LABEL: ashr_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v1.16b, v1.16b, #2
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; CHECK-NEXT: sshr v0.16b, v0.16b, #5
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%sh0 = ashr <16 x i8> %x, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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%r = and <16 x i8> %y, %sh0
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%sh1 = ashr <16 x i8> %r, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
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ret <16 x i8> %sh1
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}
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define <2 x i64> @ashr_or(<2 x i64> %x, <2 x i64> %y) nounwind {
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; CHECK-LABEL: ashr_or:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v1.2d, v1.2d, #7
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; CHECK-NEXT: sshr v0.2d, v0.2d, #12
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%sh0 = ashr <2 x i64> %x, <i64 5, i64 5>
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%r = or <2 x i64> %sh0, %y
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%sh1 = ashr <2 x i64> %r, <i64 7, i64 7>
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ret <2 x i64> %sh1
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}
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define i32 @ashr_xor(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: ashr_xor:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr w8, w0, #12
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; CHECK-NEXT: eor w0, w8, w1, asr #7
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; CHECK-NEXT: ret
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%sh0 = ashr i32 %x, 5
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%r = xor i32 %y, %sh0
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%sh1 = ashr i32 %r, 7
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ret i32 %sh1
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}
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define i32 @shr_mismatch_xor(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: shr_mismatch_xor:
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; CHECK: // %bb.0:
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; CHECK-NEXT: eor w8, w1, w0, asr #5
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; CHECK-NEXT: lsr w0, w8, #7
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; CHECK-NEXT: ret
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%sh0 = ashr i32 %x, 5
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%r = xor i32 %y, %sh0
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%sh1 = lshr i32 %r, 7
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ret i32 %sh1
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}
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define i32 @ashr_overshift_xor(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: ashr_overshift_xor:
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; CHECK: // %bb.0:
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; CHECK-NEXT: eor w8, w1, w0, asr #15
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; CHECK-NEXT: asr w0, w8, #17
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; CHECK-NEXT: ret
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%sh0 = ashr i32 %x, 15
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%r = xor i32 %y, %sh0
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%sh1 = ashr i32 %r, 17
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ret i32 %sh1
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}
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define i32 @lshr_or_extra_use(i32 %x, i32 %y, i32* %p) nounwind {
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; CHECK-LABEL: lshr_or_extra_use:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w8, w1, w0, lsr #5
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; CHECK-NEXT: lsr w0, w8, #7
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; CHECK-NEXT: str w8, [x2]
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; CHECK-NEXT: ret
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%sh0 = lshr i32 %x, 5
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%r = or i32 %sh0, %y
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store i32 %r, i32* %p
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%sh1 = lshr i32 %r, 7
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ret i32 %sh1
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}
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