forked from OSchip/llvm-project
84 lines
1.7 KiB
LLVM
84 lines
1.7 KiB
LLVM
; RUN: llc -o - %s -mtriple=aarch64-- | FileCheck %s
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; CHECK-LABEL: and1:
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; CHECK: and {{w[0-9]+}}, w0, #0xfffffffd
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define void @and1(i32 %a, i8* nocapture %p) {
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entry:
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%and = and i32 %a, 253
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%conv = trunc i32 %and to i8
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store i8 %conv, i8* %p, align 1
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ret void
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}
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; (a & 0x3dfd) | 0xffffc000
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;
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; CHECK-LABEL: and2:
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; CHECK: and {{w[0-9]+}}, w0, #0xfdfdfdfd
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define i32 @and2(i32 %a) {
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entry:
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%and = and i32 %a, 15869
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%or = or i32 %and, -16384
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ret i32 %or
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}
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; (a & 0x19) | 0xffffffc0
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;
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; CHECK-LABEL: and3:
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; CHECK: and {{w[0-9]+}}, w0, #0x99999999
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define i32 @and3(i32 %a) {
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entry:
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%and = and i32 %a, 25
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%or = or i32 %and, -64
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ret i32 %or
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}
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; (a & 0xc5600) | 0xfff1f1ff
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;
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; CHECK-LABEL: and4:
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; CHECK: and {{w[0-9]+}}, w0, #0xfffc07ff
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define i32 @and4(i32 %a) {
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entry:
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%and = and i32 %a, 787968
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%or = or i32 %and, -921089
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ret i32 %or
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}
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; Make sure we don't shrink or optimize an XOR's immediate operand if the
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; immediate is -1. Instruction selection turns (and ((xor $mask, -1), $v0)) into
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; a BIC.
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; CHECK-LABEL: xor1:
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; CHECK: mov [[R0:w[0-9]+]], #56
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; CHECK: bic {{w[0-9]+}}, [[R0]], w0, lsl #3
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define i32 @xor1(i32 %a) {
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entry:
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%shl = shl i32 %a, 3
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%xor = and i32 %shl, 56
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%and = xor i32 %xor, 56
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ret i32 %and
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}
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; Check that, when (and %t1, 129) is transformed to (and %t0, 0),
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; (xor %arg, 129) doesn't get transformed to (xor %arg, 0).
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;
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; CHECK-LABEL: PR33100:
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; CHECK: mov w[[R0:[0-9]+]], #129
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; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, x[[R0]]
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define i64 @PR33100(i64 %arg) {
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entry:
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%alloca0 = alloca i64
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store i64 8, i64* %alloca0, align 4
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%t0 = load i64, i64* %alloca0, align 4
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%t1 = shl i64 %arg, %t0
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%and0 = and i64 %t1, 129
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%xor0 = xor i64 %arg, 129
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%t2 = add i64 %and0, %xor0
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ret i64 %t2
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}
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