forked from OSchip/llvm-project
40 lines
1.1 KiB
YAML
40 lines
1.1 KiB
YAML
# RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -run-pass=aarch64-ldst-opt %s -o - | FileCheck %s
|
|
#
|
|
# The test below tests that when the AArch64 Load Store Optimization pass tries to
|
|
# convert load instructions into a ldp instruction, and when the destination
|
|
# registers are sub/super register of each other, then the convertion should not occur.
|
|
#
|
|
# For example, for the following pattern:
|
|
# ldr x10 [x9]
|
|
# ldr w10 [x9, 8],
|
|
# We cannot convert it to an ldp instruction.
|
|
#
|
|
# CHECK-NOT: LDP
|
|
# CHECK: $x10 = LDRSWui $x9, 0
|
|
# CHECK: $w10 = LDRWui $x9, 1
|
|
# CHECK: RET
|
|
---
|
|
name: test1
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x9
|
|
$x10 = LDRSWui $x9, 0 :: (load (s32))
|
|
$w10 = LDRWui $x9, 1 :: (load (s32))
|
|
RET undef $lr, implicit undef $w0
|
|
...
|
|
# CHECK-NOT: LDP
|
|
# CHECK: $w10 = LDRWui $x9, 0
|
|
# CHECK: $x10 = LDRSWui $x9, 1
|
|
# CHECK: RET
|
|
---
|
|
name: test2
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x9
|
|
$w10 = LDRWui $x9, 0 :: (load (s32))
|
|
$x10 = LDRSWui $x9, 1 :: (load (s32))
|
|
RET undef $lr, implicit undef $w0
|
|
...
|