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llvm-project/llvm/test/CodeGen
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Thomas Lively 1a57ee1276 [WebAssembly] Codegen for v128.load{32,64}_zero 
Replace the experimental clang builtins and LLVM intrinsics for these
instructions with normal instruction selection patterns. The wasm_simd128.h
intrinsics header was already using portable code for the corresponding
intrinsics, so now it produces the correct instructions.

Differential Revision: https://reviews.llvm.org/D106400
 		2021-07-21 09:02:12 -07:00
..
AArch64 AArch64: support 8 & 16-bit atomic operations in GlobalISel 2021-07-21 09:35:14 +01:00
AMDGPU [AMDGPU] Improve killed check for vgpr optimization 2021-07-21 15:24:59 +02:00
ARC
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ARM ARM: don't return by popping PC if we have to adjust the stack afterwards. 2021-07-21 09:35:14 +01:00
AVR Place the BlockAddress type in the address space of the containing function 2021-07-02 12:17:55 +01:00
BPF [BPF] Use elementtype attribute for preserve.array/struct.index intrinsics 2021-07-17 11:09:18 +02:00
Generic [llc] Default MCUseDwarfDirectory to true 2021-07-12 17:44:02 -07:00
Hexagon [DAG] Reassociate Add with Or 2021-07-07 10:21:07 +01:00
Inputs
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Lanai CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
M68k [M68k][GloballSel] LegalizerInfo implementation 2021-07-15 13:00:43 -06:00
MIR CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
MSP430
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Mips [MIPS][MSA] Regenerate basic operations test checks 2021-07-20 13:37:44 +01:00
NVPTX [NVPTX] Add select(cc,binop(),binop()) fast-math tests 2021-07-18 15:30:24 +01:00
PowerPC [PowerPC] Removing a REQUIRES line from llvm test 2021-07-21 10:52:23 -05:00
RISCV [RISCV][test] Add tests for mul optimization in the zba extension with SH*ADD 2021-07-21 10:16:56 +08:00
SPARC CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
SystemZ [SystemZ] Handle NoRegister in SystemZTargetLowering::emitMemMemWrapper(). 2021-07-19 20:04:44 +02:00
Thumb CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Thumb2 [ARM] Extend more reductions during lowering 2021-07-19 08:58:03 +01:00
VE [LegalizeTypes][VE] Don't Expand BITREVERSE/BSWAP during type legalization promotion if they will be promoted for NVT in op legalization. 2021-06-29 11:00:11 -07:00
WebAssembly [WebAssembly] Codegen for v128.load{32,64}_zero 2021-07-21 09:02:12 -07:00
WinCFGuard
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WinEH
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X86 [X86] Update MachineLoopInfo in CMOV conversion. 2021-07-21 10:53:46 +08:00
XCore Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00