forked from OSchip/llvm-project
262 lines
11 KiB
LLVM
262 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -tailcallelim -verify-dom-info -S | FileCheck %s
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; PR4323
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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; Several cases where tail call elimination should move the load above the call,
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; then eliminate the tail recursion.
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@global = external global i32 ; <i32*> [#uses=1]
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@extern_weak_global = extern_weak global i32 ; <i32*> [#uses=1]
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; This load can be moved above the call because the function won't write to it
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; and the call has no side effects.
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define fastcc i32 @raise_load_1(i32* %a_arg, i32 %a_len_arg, i32 %start_arg) nounwind readonly willreturn {
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; CHECK-LABEL: @raise_load_1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[TAILRECURSE:%.*]]
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; CHECK: tailrecurse:
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; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP10:%.*]], [[ELSE:%.*]] ]
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; CHECK-NEXT: [[START_ARG_TR:%.*]] = phi i32 [ [[START_ARG:%.*]], [[ENTRY]] ], [ [[TMP7:%.*]], [[ELSE]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sge i32 [[START_ARG_TR]], [[A_LEN_ARG:%.*]]
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; CHECK-NEXT: br i1 [[TMP2]], label [[IF:%.*]], label [[ELSE]]
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; CHECK: if:
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; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = add i32 0, [[ACCUMULATOR_TR]]
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; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]]
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; CHECK: else:
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; CHECK-NEXT: [[TMP7]] = add i32 [[START_ARG_TR]], 1
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; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ARG:%.*]], align 4
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; CHECK-NEXT: [[TMP10]] = add i32 [[TMP9]], [[ACCUMULATOR_TR]]
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; CHECK-NEXT: br label [[TAILRECURSE]]
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;
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entry:
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%tmp2 = icmp sge i32 %start_arg, %a_len_arg ; <i1> [#uses=1]
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br i1 %tmp2, label %if, label %else
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if: ; preds = %entry
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ret i32 0
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else: ; preds = %entry
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%tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
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%tmp8 = call fastcc i32 @raise_load_1(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
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%tmp9 = load i32, i32* %a_arg ; <i32> [#uses=1]
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%tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
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ret i32 %tmp10
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}
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; This load can be moved above the call because the function won't write to it
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; and the load provably can't trap.
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define fastcc i32 @raise_load_2(i32* %a_arg, i32 %a_len_arg, i32 %start_arg) readonly {
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; CHECK-LABEL: @raise_load_2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[TAILRECURSE:%.*]]
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; CHECK: tailrecurse:
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; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP10:%.*]], [[RECURSE:%.*]] ]
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; CHECK-NEXT: [[START_ARG_TR:%.*]] = phi i32 [ [[START_ARG:%.*]], [[ENTRY]] ], [ [[TMP7:%.*]], [[RECURSE]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sge i32 [[START_ARG_TR]], [[A_LEN_ARG:%.*]]
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; CHECK-NEXT: br i1 [[TMP2]], label [[IF:%.*]], label [[ELSE:%.*]]
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; CHECK: if:
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; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = add i32 0, [[ACCUMULATOR_TR]]
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; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]]
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; CHECK: else:
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; CHECK-NEXT: [[NULLCHECK:%.*]] = icmp eq i32* [[A_ARG:%.*]], null
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; CHECK-NEXT: br i1 [[NULLCHECK]], label [[UNWIND:%.*]], label [[RECURSE]]
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; CHECK: unwind:
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; CHECK-NEXT: unreachable
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; CHECK: recurse:
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; CHECK-NEXT: [[TMP7]] = add i32 [[START_ARG_TR]], 1
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; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* @global, align 4
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; CHECK-NEXT: [[TMP10]] = add i32 [[TMP9]], [[ACCUMULATOR_TR]]
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; CHECK-NEXT: br label [[TAILRECURSE]]
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;
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entry:
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%tmp2 = icmp sge i32 %start_arg, %a_len_arg ; <i1> [#uses=1]
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br i1 %tmp2, label %if, label %else
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if: ; preds = %entry
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ret i32 0
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else: ; preds = %entry
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%nullcheck = icmp eq i32* %a_arg, null ; <i1> [#uses=1]
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br i1 %nullcheck, label %unwind, label %recurse
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unwind: ; preds = %else
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unreachable
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recurse: ; preds = %else
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%tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
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%tmp8 = call fastcc i32 @raise_load_2(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
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%tmp9 = load i32, i32* @global ; <i32> [#uses=1]
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%tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
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ret i32 %tmp10
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}
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; This load can be safely moved above the call (even though it's from an
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; extern_weak global) because the call has no side effects.
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define fastcc i32 @raise_load_3(i32* %a_arg, i32 %a_len_arg, i32 %start_arg) nounwind readonly willreturn {
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; CHECK-LABEL: @raise_load_3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[TAILRECURSE:%.*]]
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; CHECK: tailrecurse:
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; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP10:%.*]], [[ELSE:%.*]] ]
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; CHECK-NEXT: [[START_ARG_TR:%.*]] = phi i32 [ [[START_ARG:%.*]], [[ENTRY]] ], [ [[TMP7:%.*]], [[ELSE]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sge i32 [[START_ARG_TR]], [[A_LEN_ARG:%.*]]
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; CHECK-NEXT: br i1 [[TMP2]], label [[IF:%.*]], label [[ELSE]]
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; CHECK: if:
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; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = add i32 0, [[ACCUMULATOR_TR]]
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; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]]
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; CHECK: else:
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; CHECK-NEXT: [[TMP7]] = add i32 [[START_ARG_TR]], 1
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; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* @extern_weak_global, align 4
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; CHECK-NEXT: [[TMP10]] = add i32 [[TMP9]], [[ACCUMULATOR_TR]]
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; CHECK-NEXT: br label [[TAILRECURSE]]
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;
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entry:
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%tmp2 = icmp sge i32 %start_arg, %a_len_arg ; <i1> [#uses=1]
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br i1 %tmp2, label %if, label %else
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if: ; preds = %entry
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ret i32 0
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else: ; preds = %entry
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%tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
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%tmp8 = call fastcc i32 @raise_load_3(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
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%tmp9 = load i32, i32* @extern_weak_global ; <i32> [#uses=1]
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%tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
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ret i32 %tmp10
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}
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; The second load can be safely moved above the call even though it's from an
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; unknown pointer (which normally means it might trap) because the first load
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; proves it doesn't trap.
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define fastcc i32 @raise_load_4(i32* %a_arg, i32 %a_len_arg, i32 %start_arg) readonly {
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; CHECK-LABEL: @raise_load_4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[TAILRECURSE:%.*]]
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; CHECK: tailrecurse:
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; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP10:%.*]], [[RECURSE:%.*]] ]
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; CHECK-NEXT: [[A_LEN_ARG_TR:%.*]] = phi i32 [ [[A_LEN_ARG:%.*]], [[ENTRY]] ], [ [[FIRST:%.*]], [[RECURSE]] ]
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; CHECK-NEXT: [[START_ARG_TR:%.*]] = phi i32 [ [[START_ARG:%.*]], [[ENTRY]] ], [ [[TMP7:%.*]], [[RECURSE]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sge i32 [[START_ARG_TR]], [[A_LEN_ARG_TR]]
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; CHECK-NEXT: br i1 [[TMP2]], label [[IF:%.*]], label [[ELSE:%.*]]
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; CHECK: if:
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; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = add i32 0, [[ACCUMULATOR_TR]]
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; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]]
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; CHECK: else:
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; CHECK-NEXT: [[NULLCHECK:%.*]] = icmp eq i32* [[A_ARG:%.*]], null
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; CHECK-NEXT: br i1 [[NULLCHECK]], label [[UNWIND:%.*]], label [[RECURSE]]
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; CHECK: unwind:
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; CHECK-NEXT: unreachable
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; CHECK: recurse:
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; CHECK-NEXT: [[TMP7]] = add i32 [[START_ARG_TR]], 1
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; CHECK-NEXT: [[FIRST]] = load i32, i32* [[A_ARG]], align 4
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; CHECK-NEXT: [[SECOND:%.*]] = load i32, i32* [[A_ARG]], align 4
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; CHECK-NEXT: [[TMP10]] = add i32 [[SECOND]], [[ACCUMULATOR_TR]]
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; CHECK-NEXT: br label [[TAILRECURSE]]
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;
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entry:
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%tmp2 = icmp sge i32 %start_arg, %a_len_arg ; <i1> [#uses=1]
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br i1 %tmp2, label %if, label %else
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if: ; preds = %entry
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ret i32 0
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else: ; preds = %entry
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%nullcheck = icmp eq i32* %a_arg, null ; <i1> [#uses=1]
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br i1 %nullcheck, label %unwind, label %recurse
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unwind: ; preds = %else
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unreachable
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recurse: ; preds = %else
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%tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
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%first = load i32, i32* %a_arg ; <i32> [#uses=1]
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%tmp8 = call fastcc i32 @raise_load_4(i32* %a_arg, i32 %first, i32 %tmp7) ; <i32> [#uses=1]
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%second = load i32, i32* %a_arg ; <i32> [#uses=1]
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%tmp10 = add i32 %second, %tmp8 ; <i32> [#uses=1]
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ret i32 %tmp10
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}
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; This load can be moved above the call because the function won't write to it
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; and the a_arg is dereferenceable.
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define fastcc i32 @raise_load_5(i32* dereferenceable(4) align 4 %a_arg, i32 %a_len_arg, i32 %start_arg) readonly nofree nosync {
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; CHECK-LABEL: @raise_load_5(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[TAILRECURSE:%.*]]
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; CHECK: tailrecurse:
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; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP10:%.*]], [[ELSE:%.*]] ]
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; CHECK-NEXT: [[START_ARG_TR:%.*]] = phi i32 [ [[START_ARG:%.*]], [[ENTRY]] ], [ [[TMP7:%.*]], [[ELSE]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sge i32 [[START_ARG_TR]], [[A_LEN_ARG:%.*]]
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; CHECK-NEXT: br i1 [[TMP2]], label [[IF:%.*]], label [[ELSE]]
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; CHECK: if:
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; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = add i32 0, [[ACCUMULATOR_TR]]
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; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]]
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; CHECK: else:
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; CHECK-NEXT: [[TMP7]] = add i32 [[START_ARG_TR]], 1
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; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ARG:%.*]], align 4
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; CHECK-NEXT: [[TMP10]] = add i32 [[TMP9]], [[ACCUMULATOR_TR]]
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; CHECK-NEXT: br label [[TAILRECURSE]]
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;
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entry:
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%tmp2 = icmp sge i32 %start_arg, %a_len_arg ; <i1> [#uses=1]
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br i1 %tmp2, label %if, label %else
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if: ; preds = %entry
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ret i32 0
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else: ; preds = %entry
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%tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
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%tmp8 = call fastcc i32 @raise_load_5(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
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%tmp9 = load i32, i32* %a_arg ; <i32> [#uses=1]
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%tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
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ret i32 %tmp10
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}
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; This load can be moved above the call because the function call does not write to the memory the load
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; is accessing and the load is safe to speculate.
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define fastcc i32 @raise_load_6(i32* %a_arg, i32 %a_len_arg, i32 %start_arg) nounwind {
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; CHECK-LABEL: @raise_load_6(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[S:%.*]] = alloca i32, align 4
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; CHECK-NEXT: br label [[TAILRECURSE:%.*]]
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; CHECK: tailrecurse:
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; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP10:%.*]], [[ELSE:%.*]] ]
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; CHECK-NEXT: [[START_ARG_TR:%.*]] = phi i32 [ [[START_ARG:%.*]], [[ENTRY]] ], [ [[TMP7:%.*]], [[ELSE]] ]
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; CHECK-NEXT: store i32 4, i32* [[S]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sge i32 [[START_ARG_TR]], [[A_LEN_ARG:%.*]]
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; CHECK-NEXT: br i1 [[TMP2]], label [[IF:%.*]], label [[ELSE]]
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; CHECK: if:
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; CHECK-NEXT: store i32 1, i32* [[A_ARG:%.*]], align 4
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; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = add i32 0, [[ACCUMULATOR_TR]]
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; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]]
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; CHECK: else:
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; CHECK-NEXT: [[TMP7]] = add i32 [[START_ARG_TR]], 1
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; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[S]], align 4
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; CHECK-NEXT: [[TMP10]] = add i32 [[TMP9]], [[ACCUMULATOR_TR]]
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; CHECK-NEXT: br label [[TAILRECURSE]]
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;
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entry:
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%s = alloca i32
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store i32 4, i32* %s
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%tmp2 = icmp sge i32 %start_arg, %a_len_arg ; <i1> [#uses=1]
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br i1 %tmp2, label %if, label %else
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if: ; preds = %entry
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store i32 1, i32* %a_arg
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ret i32 0
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else: ; preds = %entry
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%tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
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%tmp8 = call fastcc i32 @raise_load_6(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
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%tmp9 = load i32, i32* %s ; <i32> [#uses=1]
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%tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
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ret i32 %tmp10
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}
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