Ayke van Laethem 4f6d7985d4 [AVR] Add register aliases XL, YH, etc ... These aliases are sometimes used in assembly code and make the code more readable. They are supported by avr-gcc too. Differential Revision: https://reviews.llvm.org/D96492		2021-03-03 15:36:05 +01:00
..
out-of-range-fixups	…
dwarf-asm-no-code.s	…
hex-immediates.s	[AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex	2020-07-12 08:14:52 -07:00
inst-adc.s	…
inst-add.s	…
inst-adiw.s	[AVR] Disassemble double register instructions	2020-06-23 02:18:04 +02:00
inst-and.s	…
inst-andi.s	…
inst-asr.s	[AVR] Decode single register instructions	2020-06-23 02:17:15 +02:00
inst-bld.s	…
inst-brbc.s	…
inst-brbs.s	…
inst-break.s	…
inst-bst.s	…
inst-call.s	[AVR] Implement disassembly of 32-bit instructions	2020-06-18 11:26:58 +02:00
inst-cbi.s	…
inst-cbr.s	…
inst-clr.s	…
inst-com.s	[AVR] Decode single register instructions	2020-06-23 02:17:15 +02:00
inst-cp.s	…
inst-cpc.s	…
inst-cpi.s	…
inst-cpse.s	…
inst-dec.s	[AVR] Decode single register instructions	2020-06-23 02:17:15 +02:00
inst-des.s	…
inst-eicall.s	…
inst-eijmp.s	…
inst-elpm.s	[AVR] Disassemble instructions with fixed Z operand	2020-06-23 02:17:53 +02:00
inst-eor.s	…
inst-family-cond-branch.s	…
inst-family-set-clr-flag.s	…
inst-fmul.s	[AVR] Disassemble multiplication instructions	2020-06-23 02:17:37 +02:00
inst-fmuls.s	[AVR] Disassemble multiplication instructions	2020-06-23 02:17:37 +02:00
inst-fmulsu.s	[AVR] Disassemble multiplication instructions	2020-06-23 02:17:37 +02:00
inst-icall.s	…
inst-ijmp.s	…
inst-in.s	…
inst-inc.s	[AVR] Decode single register instructions	2020-06-23 02:17:15 +02:00
inst-jmp.s	[AVR] Implement disassembly of 32-bit instructions	2020-06-18 11:26:58 +02:00
inst-lac.s	[AVR] Disassemble instructions with fixed Z operand	2020-06-23 02:17:53 +02:00
inst-las.s	[AVR] Disassemble instructions with fixed Z operand	2020-06-23 02:17:53 +02:00
inst-lat.s	[AVR] Disassemble instructions with fixed Z operand	2020-06-23 02:17:53 +02:00
inst-ld.s	…
inst-ldd.s	…
inst-ldi.s	…
inst-lds.s	[AVR] Implement disassembly of 32-bit instructions	2020-06-18 11:26:58 +02:00
inst-lpm.s	[AVR] Disassemble instructions with fixed Z operand	2020-06-23 02:17:53 +02:00
inst-lsl.s	…
inst-lsr.s	[AVR] Decode single register instructions	2020-06-23 02:17:15 +02:00
inst-mov.s	…
inst-movw.s	[AVR] Disassemble double register instructions	2020-06-23 02:18:04 +02:00
inst-mul.s	…
inst-muls.s	[AVR] Disassemble multiplication instructions	2020-06-23 02:17:37 +02:00
inst-mulsu.s	[AVR] Disassemble multiplication instructions	2020-06-23 02:17:37 +02:00
inst-neg.s	[AVR] Decode single register instructions	2020-06-23 02:17:15 +02:00
inst-nop.s	…
inst-or.s	…
inst-ori.s	…
inst-out.s	…
inst-pop.s	[AVR] Decode single register instructions	2020-06-23 02:17:15 +02:00
inst-push.s	[AVR] Decode single register instructions	2020-06-23 02:17:15 +02:00
inst-rcall.s	…
inst-ret.s	…
inst-reti.s	…
inst-rjmp.s	…
inst-rol.s	…
inst-ror.s	[AVR] Decode single register instructions	2020-06-23 02:17:15 +02:00
inst-sbc.s	…
inst-sbci.s	…
inst-sbi.s	…
inst-sbic.s	…
inst-sbis.s	…
inst-sbiw.s	[AVR] Disassemble double register instructions	2020-06-23 02:18:04 +02:00
inst-sbr.s	…
inst-sbrc.s	…
inst-sbrs.s	…
inst-ser.s	…
inst-sleep.s	…
inst-spm.s	[AVR] Disassemble instructions with fixed Z operand	2020-06-23 02:17:53 +02:00
inst-st.s	…
inst-std.s	…
inst-sts.s	[AVR] Implement disassembly of 32-bit instructions	2020-06-18 11:26:58 +02:00
inst-sub.s	…
inst-subi.s	…
inst-swap.s	[AVR] Decode single register instructions	2020-06-23 02:17:15 +02:00
inst-tst.s	…
inst-wdr.s	…
inst-xch.s	[AVR] Disassemble instructions with fixed Z operand	2020-06-23 02:17:53 +02:00
lit.local.cfg	…
modifiers.s	…
registers.s	[AVR] Add register aliases XL, YH, etc	2021-03-03 15:36:05 +01:00
relocations-abs.s	…
relocations.s	[AVR] Fix global references to function symbols	2021-02-10 00:40:49 +13:00
symbol_relocation.s	…
syntax-reg-int-literal.s	…
syntax-reg-pair.s	…