forked from OSchip/llvm-project
58 lines
1.9 KiB
ArmAsm
58 lines
1.9 KiB
ArmAsm
// RUN: not llvm-mc -triple arm-eabi -mattr=+v5te %s -o /dev/null 2>&1 | FileCheck %s
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//
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// rdar://14479793
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ldrd r1, r2, [pc, #0]
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ldrd r1, r2, [r3, #4]
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ldrd r1, r2, [r3], #4
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ldrd r1, r2, [r3, #4]!
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ldrd r1, r2, [r3, -r4]!
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ldrd r1, r2, [r3, r4]
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ldrd r1, r2, [r3], r4
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// CHECK: error: Rt must be even-numbered
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// CHECK: error: Rt must be even-numbered
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// CHECK: error: Rt must be even-numbered
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// CHECK: error: Rt must be even-numbered
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// CHECK: error: Rt must be even-numbered
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// CHECK: error: Rt must be even-numbered
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// CHECK: error: Rt must be even-numbered
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ldrd r0, r3, [pc, #0]
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ldrd r0, r3, [r4, #4]
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ldrd r0, r3, [r4], #4
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ldrd r0, r3, [r4, #4]!
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ldrd r0, r3, [r4, -r5]!
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ldrd r0, r3, [r4, r5]
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ldrd r0, r3, [r4], r5
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// CHECK: error: destination operands must be sequential
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// CHECK: error: destination operands must be sequential
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// CHECK: error: destination operands must be sequential
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// CHECK: error: destination operands must be sequential
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// CHECK: error: destination operands must be sequential
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// CHECK: error: destination operands must be sequential
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// CHECK: error: destination operands must be sequential
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ldrd lr, pc, [pc, #0]
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ldrd lr, pc, [r3, #4]
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ldrd lr, pc, [r3], #4
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ldrd lr, pc, [r3, #4]!
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ldrd lr, pc, [r3, -r4]!
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ldrd lr, pc, [r3, r4]
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ldrd lr, pc, [r3], r4
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// CHECK: error: Rt can't be R14
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// CHECK: error: Rt can't be R14
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// CHECK: error: Rt can't be R14
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// CHECK: error: Rt can't be R14
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// CHECK: error: Rt can't be R14
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// CHECK: error: Rt can't be R14
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// CHECK: error: Rt can't be R14
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ldrd r0, r1, [r0], #4
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ldrd r0, r1, [r1], #4
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ldrd r0, r1, [r0, #4]!
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ldrd r0, r1, [r1, #4]!
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// CHECK: error: base register needs to be different from destination registers
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// CHECK: error: base register needs to be different from destination registers
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// CHECK: error: base register needs to be different from destination registers
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// CHECK: error: base register needs to be different from destination registers
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