forked from OSchip/llvm-project
265 lines
8.2 KiB
C++
265 lines
8.2 KiB
C++
//===-- R600ControlFlowFinalizer.cpp - Finalize Control Flow Inst----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass compute turns all control flow pseudo instructions into native one
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/// computing their address on the fly ; it also sets STACK_SIZE info.
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "R600RegisterInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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namespace llvm {
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class R600ControlFlowFinalizer : public MachineFunctionPass {
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private:
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static char ID;
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const R600InstrInfo *TII;
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unsigned MaxFetchInst;
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bool isFetch(const MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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case AMDGPU::TEX_VTX_CONSTBUF:
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case AMDGPU::TEX_VTX_TEXBUF:
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case AMDGPU::TEX_LD:
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case AMDGPU::TEX_GET_TEXTURE_RESINFO:
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case AMDGPU::TEX_GET_GRADIENTS_H:
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case AMDGPU::TEX_GET_GRADIENTS_V:
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case AMDGPU::TEX_SET_GRADIENTS_H:
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case AMDGPU::TEX_SET_GRADIENTS_V:
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case AMDGPU::TEX_SAMPLE:
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case AMDGPU::TEX_SAMPLE_C:
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case AMDGPU::TEX_SAMPLE_L:
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case AMDGPU::TEX_SAMPLE_C_L:
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case AMDGPU::TEX_SAMPLE_LB:
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case AMDGPU::TEX_SAMPLE_C_LB:
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case AMDGPU::TEX_SAMPLE_G:
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case AMDGPU::TEX_SAMPLE_C_G:
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case AMDGPU::TXD:
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case AMDGPU::TXD_SHADOW:
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return true;
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default:
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return false;
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}
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}
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bool IsTrivialInst(MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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case AMDGPU::KILL:
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case AMDGPU::RETURN:
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return true;
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default:
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return false;
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}
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}
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MachineBasicBlock::iterator
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MakeFetchClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned CfAddress) const {
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MachineBasicBlock::iterator ClauseHead = I;
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unsigned AluInstCount = 0;
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for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
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if (IsTrivialInst(I))
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continue;
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if (!isFetch(I))
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break;
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AluInstCount ++;
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if (AluInstCount > MaxFetchInst)
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break;
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}
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BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead),
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TII->get(AMDGPU::CF_TC))
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.addImm(CfAddress) // ADDR
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.addImm(AluInstCount); // COUNT
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return I;
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}
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void CounterPropagateAddr(MachineInstr *MI, unsigned Addr) const {
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switch (MI->getOpcode()) {
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case AMDGPU::WHILE_LOOP:
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MI->getOperand(0).setImm(Addr + 1);
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break;
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default:
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MI->getOperand(0).setImm(Addr);
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break;
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}
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}
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void CounterPropagateAddr(std::set<MachineInstr *> MIs, unsigned Addr)
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const {
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for (std::set<MachineInstr *>::iterator It = MIs.begin(), E = MIs.end();
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It != E; ++It) {
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MachineInstr *MI = *It;
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CounterPropagateAddr(MI, Addr);
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}
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}
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public:
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R600ControlFlowFinalizer(TargetMachine &tm) : MachineFunctionPass(ID),
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TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) {
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const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>();
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if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD4XXX)
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MaxFetchInst = 8;
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else
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MaxFetchInst = 16;
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}
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virtual bool runOnMachineFunction(MachineFunction &MF) {
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unsigned MaxStack = 0;
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unsigned CurrentStack = 0;
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for (MachineFunction::iterator MB = MF.begin(), ME = MF.end(); MB != ME;
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++MB) {
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MachineBasicBlock &MBB = *MB;
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unsigned CfCount = 0;
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std::vector<std::pair<unsigned, std::set<MachineInstr *> > > LoopStack;
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std::vector<std::pair<unsigned, MachineInstr *> > IfThenElseStack;
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R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
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if (MFI->ShaderType == 1) {
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BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
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TII->get(AMDGPU::CF_CALL_FS));
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CfCount++;
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}
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E;) {
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if (isFetch(I)) {
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I = MakeFetchClause(MBB, I, 0);
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CfCount++;
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continue;
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}
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MachineBasicBlock::iterator MI = I;
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I++;
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switch (MI->getOpcode()) {
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case AMDGPU::CF_ALU_PUSH_BEFORE:
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CurrentStack++;
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MaxStack = std::max(MaxStack, CurrentStack);
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case AMDGPU::KILLGT:
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case AMDGPU::CF_ALU:
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CfCount++;
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break;
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case AMDGPU::WHILELOOP: {
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CurrentStack++;
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MaxStack = std::max(MaxStack, CurrentStack);
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MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
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TII->get(AMDGPU::WHILE_LOOP))
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.addImm(0);
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std::pair<unsigned, std::set<MachineInstr *> > Pair(CfCount,
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std::set<MachineInstr *>());
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Pair.second.insert(MIb);
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LoopStack.push_back(Pair);
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MI->eraseFromParent();
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CfCount++;
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break;
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}
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case AMDGPU::ENDLOOP: {
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CurrentStack--;
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std::pair<unsigned, std::set<MachineInstr *> > Pair =
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LoopStack.back();
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LoopStack.pop_back();
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CounterPropagateAddr(Pair.second, CfCount);
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BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::END_LOOP))
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.addImm(Pair.first + 1);
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MI->eraseFromParent();
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CfCount++;
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break;
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}
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case AMDGPU::IF_PREDICATE_SET: {
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MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
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TII->get(AMDGPU::CF_JUMP))
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.addImm(0)
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.addImm(0);
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std::pair<unsigned, MachineInstr *> Pair(CfCount, MIb);
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IfThenElseStack.push_back(Pair);
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MI->eraseFromParent();
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CfCount++;
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break;
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}
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case AMDGPU::ELSE: {
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std::pair<unsigned, MachineInstr *> Pair = IfThenElseStack.back();
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IfThenElseStack.pop_back();
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CounterPropagateAddr(Pair.second, CfCount);
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MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
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TII->get(AMDGPU::CF_ELSE))
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.addImm(0)
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.addImm(1);
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std::pair<unsigned, MachineInstr *> NewPair(CfCount, MIb);
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IfThenElseStack.push_back(NewPair);
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MI->eraseFromParent();
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CfCount++;
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break;
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}
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case AMDGPU::ENDIF: {
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CurrentStack--;
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std::pair<unsigned, MachineInstr *> Pair = IfThenElseStack.back();
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IfThenElseStack.pop_back();
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CounterPropagateAddr(Pair.second, CfCount + 1);
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BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::POP))
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.addImm(CfCount + 1)
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.addImm(1);
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MI->eraseFromParent();
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CfCount++;
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break;
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}
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case AMDGPU::PREDICATED_BREAK: {
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CurrentStack--;
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CfCount += 3;
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BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::CF_JUMP))
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.addImm(CfCount)
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.addImm(1);
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MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
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TII->get(AMDGPU::LOOP_BREAK))
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.addImm(0);
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BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::POP))
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.addImm(CfCount)
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.addImm(1);
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LoopStack.back().second.insert(MIb);
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MI->eraseFromParent();
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break;
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}
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case AMDGPU::CONTINUE: {
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MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
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TII->get(AMDGPU::CF_CONTINUE))
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.addImm(CfCount);
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LoopStack.back().second.insert(MIb);
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MI->eraseFromParent();
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CfCount++;
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break;
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}
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default:
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break;
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}
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}
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BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
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TII->get(AMDGPU::STACK_SIZE))
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.addImm(MaxStack);
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}
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return false;
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}
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const char *getPassName() const {
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return "R600 Control Flow Finalizer Pass";
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}
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};
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char R600ControlFlowFinalizer::ID = 0;
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}
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llvm::FunctionPass *llvm::createR600ControlFlowFinalizer(TargetMachine &TM) {
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return new R600ControlFlowFinalizer(TM);
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}
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