Douglas Yung d622612e61 Relax newly added opcode checks to check only for a number instead of a specific opcode.		2020-03-25 20:15:33 -07:00
..
AArch64	Relax newly added opcode checks to check only for a number instead of a specific opcode.	2020-03-25 20:15:33 -07:00
AMDGPU	[AMDGPU] Fixed function traversal in attribute propagation	2020-03-25 18:47:09 -07:00
ARC	…
ARM	[ARM] Move ConstantIsland and LowOverheadLoops Passes.	2020-03-25 16:49:21 +01:00
AVR	[AVR] Fix incorrect register state for LDRdPtr	2020-03-03 17:34:54 +08:00
BPF	[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options	2020-03-15 17:46:23 -07:00
Generic	[NFC] Add missing REQUIRES clause to a test	2020-03-18 16:35:10 +03:00
Hexagon	Revert "Include static prof data when collecting loop BBs"	2020-03-24 09:41:16 -07:00
Inputs	…
Lanai	…
MIR	[AMDGPU] Move frame pointer from s34 to s33	2020-03-19 15:35:16 -04:00
MSP430	…
Mips	[GlobalISel] combine G_TRUNC with G_MERGE_VALUES	2020-03-16 14:42:01 +01:00
NVPTX	ARM: Fixup some tests using denormal-fp-math attribute	2020-03-10 14:02:06 -04:00
PowerPC	[PowerPC][AIX] ByVal formal arguments in a single register.	2020-03-25 11:09:40 -04:00
RISCV	[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w	2020-03-20 09:42:24 +00:00
SPARC	[Sparc] Fix incorrect operand for matching CMPri pattern	2020-03-02 11:36:32 +08:00
SystemZ	[SystemZ] Improve foldMemoryOperandImpl()	2020-03-25 16:21:08 +01:00
Thumb	[DAGCombine] Skip PostInc combine with later users	2020-03-23 08:39:53 +00:00
Thumb2	[ARM,CDE] Implement predicated Q-register CDE intrinsics	2020-03-25 17:08:19 +00:00
VE	[VE] Target-specific bit size for sjljehprepare	2020-03-10 17:51:16 +01:00
WebAssembly	[WebAssembly] Support swiftself and swifterror for WebAssembly target	2020-03-19 17:39:52 -07:00
WinCFGuard	…
WinEH	…
X86	[X86][AVX] Combine shuffles to TRUNCATE/VTRUNC patterns	2020-03-25 17:41:51 +00:00
XCore	[XCore] Add instruction pattern for bitrev	2020-02-21 09:28:49 +08:00