Sagar Thakur 48973d21e1 [MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISA ... Summary: The assembler was picking the wrong JR variant because the pre-R6 one was still enabled at R6. Author: nitesh.jain Reviewers: vkalintiris, dsanders Subscribers: dsanders, llvm-commits, mohit.bhakkad, sagar, bhushan, jaydeep Differential: D18387 llvm-svn: 265134		2016-04-01 11:55:33 +00:00
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invalid-mips1-wrong-error.s	[mips] Range check simm9 and fix a bug this revealed.	2016-03-31 13:15:23 +00:00
invalid-mips1.s	[mips] Marked the ADDi instruction aliases as not available in Mips32R6 and Mips64R6.	2014-09-16 09:26:09 +00:00
invalid-mips2.s	[mips] Add support for COP1's Branch-On-Cond-Likely instructions	2014-10-17 14:08:28 +00:00
invalid-mips3-wrong-error.s	[mips] Range check simm9 and fix a bug this revealed.	2016-03-31 13:15:23 +00:00
invalid-mips3.s	…
invalid-mips4-wrong-error.s	[mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and SWE instructions	2015-09-16 09:14:35 +00:00
invalid-mips4.s	[mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and SWE instructions	2015-09-16 09:14:35 +00:00
invalid-mips5-wrong-error.s	[mips] Improve the error messages given by MipsAsmParser.	2014-09-16 15:00:52 +00:00
invalid-mips5.s	…
invalid-mips32-wrong-error.s	[mips] Add support for COP1's Branch-On-Cond-Likely instructions	2014-10-17 14:08:28 +00:00
invalid-mips64.s	…
invalid.s	[mips] Invalid tests for MTC0, MTC2, MFC0, MFC2, DMTC0, DMFC0 MIPS instructions	2016-03-11 08:00:11 +00:00
relocations.s	[mips64] Emit correct addend for some PC-relative relocations	2015-06-23 13:54:42 +00:00
valid-xfail.s	…
valid.s	[MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISA	2016-04-01 11:55:33 +00:00