Daniel Sanders a45d3e439f [mips] Trivial corrections to range checked immediates. ... Summary: SYNC has a 5-bit unsigned immediate. Move MIPS16-specific pcrel16 operand to Mips16 files. Reviewers: vkalintiris Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18755 llvm-svn: 265947		2016-04-11 15:20:40 +00:00
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AArch64	AArch64: support .cpu directive	2016-04-02 19:29:52 +00:00
AMDGPU	[AMDGPU] AsmParser: disable DPP for unsupported instructions. New dpp tests. Fix v_nop_dpp.	2016-04-06 13:29:59 +00:00
ARM	[ARM] Avoid switching ARM/Thumb mode on .arch/.cpu directive	2016-04-11 13:06:28 +00:00
AsmParser	[MCParser] Accept uppercase radix variants 0X and 0B	2016-03-18 18:22:07 +00:00
COFF	[codeview] Dump def range lengths in hex	2016-02-11 23:40:14 +00:00
Disassembler	[SystemZ] Add SVC instruction	2016-04-11 14:35:39 +00:00
ELF	[MC] support TLSDESC and TLSCALL / GNU2 tls dialect	2016-04-09 20:32:33 +00:00
Hexagon	Revert r265817	2016-04-08 18:15:37 +00:00
Lanai	[lanai] isBrImm should accept any non-constant immediate.	2016-03-31 17:58:55 +00:00
MachO	Add missing emissionKind flags to the DICompileUnits of several old testcases.	2016-04-01 22:18:43 +00:00
Markup	…
Mips	[mips] Trivial corrections to range checked immediates.	2016-04-11 15:20:40 +00:00
PowerPC	[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance	2016-04-06 01:47:02 +00:00
Sparc	Sparc: silently ignore .proc assembler directive	2016-03-28 14:00:11 +00:00
SystemZ	[SystemZ] Add SVC instruction	2016-04-11 14:35:39 +00:00
X86	[X86] Restrict max long nop length for Lakemont.	2016-04-11 10:07:36 +00:00