| .. |
|
AsmParser
|
[RISCV] Implement pseudo instructions for load/store from a symbol address.
|
2019-02-20 03:31:32 +00:00 |
|
Disassembler
|
[RISCV] Replace incorrect use of sizeof with array_lengthof
|
2019-03-13 09:22:57 +00:00 |
|
InstPrinter
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
MCTargetDesc
|
[RISCV][MC] Find matching pcrel_hi fixup in more cases.
|
2019-03-12 18:14:16 +00:00 |
|
TargetInfo
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
Utils
|
[RISCV] Support -target-abi at the MC layer and for codegen
|
2019-03-09 09:28:06 +00:00 |
|
CMakeLists.txt
|
[RISCV] Support named operands for CSR instructions.
|
2018-10-04 21:50:54 +00:00 |
|
LLVMBuild.txt
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCV.h
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCV.td
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCVAsmPrinter.cpp
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCVCallingConv.td
|
[RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor RISCVRegisterInfo refactoring
|
2019-03-14 08:28:48 +00:00 |
|
RISCVExpandPseudoInsts.cpp
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCVFrameLowering.cpp
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCVFrameLowering.h
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCVISelDAGToDAG.cpp
|
[RISCV][NFC] Add break to case statement in RISCVDAGToDAGISel::Select
|
2019-01-22 07:22:00 +00:00 |
|
RISCVISelLowering.cpp
|
[RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()
|
2019-03-11 20:43:29 +00:00 |
|
RISCVISelLowering.h
|
[RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A
|
2019-03-11 21:41:22 +00:00 |
|
RISCVInstrFormats.td
|
[RISCV] Implement pseudo instructions for load/store from a symbol address.
|
2019-02-20 03:31:32 +00:00 |
|
RISCVInstrFormatsC.td
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCVInstrInfo.cpp
|
[RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()
|
2019-03-11 20:43:29 +00:00 |
|
RISCVInstrInfo.h
|
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
|
2019-01-25 20:22:49 +00:00 |
|
RISCVInstrInfo.td
|
[RISCV] Add implied zero offset load/store alias patterns
|
2019-02-21 14:09:34 +00:00 |
|
RISCVInstrInfoA.td
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCVInstrInfoC.td
|
[RISCV] Add implied zero offset load/store alias patterns
|
2019-02-21 14:09:34 +00:00 |
|
RISCVInstrInfoD.td
|
[RISCV] Add implied zero offset load/store alias patterns
|
2019-02-21 14:09:34 +00:00 |
|
RISCVInstrInfoF.td
|
[RISCV] Add implied zero offset load/store alias patterns
|
2019-02-21 14:09:34 +00:00 |
|
RISCVInstrInfoM.td
|
[RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M
|
2019-01-25 05:11:34 +00:00 |
|
RISCVMCInstLower.cpp
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCVMachineFunctionInfo.h
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCVMergeBaseOffset.cpp
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCVRegisterInfo.cpp
|
[RISCV] Fix rL356123
|
2019-03-14 08:31:35 +00:00 |
|
RISCVRegisterInfo.h
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCVRegisterInfo.td
|
[RISCV] Allow fp as an alias of s0
|
2019-03-11 21:35:26 +00:00 |
|
RISCVSubtarget.cpp
|
[RISCV] Support -target-abi at the MC layer and for codegen
|
2019-03-09 09:28:06 +00:00 |
|
RISCVSubtarget.h
|
[RISCV] Support -target-abi at the MC layer and for codegen
|
2019-03-09 09:28:06 +00:00 |
|
RISCVSystemOperands.td
|
[RISCV] Allow access to FP CSRs without F extension
|
2019-03-08 23:01:08 +00:00 |
|
RISCVTargetMachine.cpp
|
[RISCV] Support -target-abi at the MC layer and for codegen
|
2019-03-09 09:28:06 +00:00 |
|
RISCVTargetMachine.h
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCVTargetObjectFile.cpp
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
|
RISCVTargetObjectFile.h
|
Update the file headers across all of the LLVM projects in the monorepo
|
2019-01-19 08:50:56 +00:00 |
fec503acb6