llvm-project/llvm/test/MC
James Molloy 88cad7e5cf [SimplifyCFG] Handle tail-sinking of more than 2 incoming branches
This was a real restriction in the original version of SinkIfThenCodeToEnd. Now it's been rewritten, the restriction can be lifted.

As part of this, we handle a very common and useful case where one of the incoming branches is actually conditional. Consider:

   if (a)
     x(1);
   else if (b)
     x(2);

This produces the following CFG:

         [if]
        /    \
      [x(1)] [if]
        |     | \
        |     |  \
        |  [x(2)] |
         \    |  /
          [ end ]

[end] has two unconditional predecessor arcs and one conditional. The conditional refers to the implicit empty 'else' arc. This same pattern can also be caused by an empty default block in a switch.

We can't sink the call to x() down to end because no call to x() happens on the third incoming arc (assume that x() has sideeffects for the sake of argument; if something is safe to speculate we could indeed sink nevertheless but this cannot happen in the general case and causes many extra selects).

We are now able to detect this case and split off the unconditional arcs to a common successor:

         [if]
        /    \
      [x(1)] [if]
        |     | \
        |     |  \
        |  [x(2)] |
         \   /    |
     [sink.split] |
           \     /
           [ end ]

Now we can sink the call to x() into %sink.split. This can cause significant code simplification in many testcases.

llvm-svn: 280364
2016-09-01 12:58:13 +00:00
..
AArch64 AArch64: TableGenerate system instruction operands. 2016-07-05 21:23:04 +00:00
AMDGPU AMDGPU: Improve error reporting for maximum branch distance 2016-08-27 00:21:22 +00:00
ARM [SimplifyCFG] Handle tail-sinking of more than 2 incoming branches 2016-09-01 12:58:13 +00:00
AsmParser [MC] Support .dc directives in assembler parser 2016-08-23 21:34:53 +00:00
COFF [codeview] Shrink inlined call site line info tables 2016-07-14 23:47:15 +00:00
Disassembler [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations 2016-08-22 12:17:59 +00:00
ELF Add initial support for R_386_GOT32X. 2016-07-06 21:19:11 +00:00
Hexagon Remove redundant -mattr options from llvm-objdump commands. 2016-06-16 15:47:19 +00:00
Lanai [lanai] Add more tests for assembly of conditional ALU ops 2016-07-11 17:58:16 +00:00
MachO CodeGen: Use PLT relocations for relative references to unnamed_addr functions. 2016-04-22 20:40:10 +00:00
Markup
Mips [mips][ias] Support .dtprel[d]word and .tprel[d]word directives 2016-08-22 16:18:42 +00:00
PowerPC Add aliases for mfvrsave/mtvrsave. 2016-06-09 23:27:48 +00:00
Sparc Don't pass a Reloc::Model to MC. 2016-05-18 11:58:50 +00:00
SystemZ [SystemZ] Add support for the .insn directive 2016-08-08 15:13:08 +00:00
X86 [X86] Don't allow DR8-DR15 to be assembled in 32-bit mode. Add missing test for CR8-CR15. 2016-08-27 17:13:34 +00:00