llvm-project/llvm/test/CodeGen/RISCV
Shiva Chen 078bec6c48 [RISCV] Support fast calling convention
LLVM may annotate the function with fastcc if there has only one caller
and there're no other caller out of the module and the function is not
naked or contain variable arguments.

The fastcc functions could pass the arguments by the caller saved registers.

Differential Revision: https://reviews.llvm.org/D68559

llvm-svn: 374857
2019-10-15 02:04:29 +00:00
..
GlobalISel [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
add-before-shl.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
addc-adde-sube-subc.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
addcarry.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
align.ll
alloca.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
alu8.ll
alu16.ll
alu32.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
alu64.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
analyze-branch.ll
arith-with-overflow.ll [TargetLowering] Simplify expansion of S{ADD,SUB}O 2019-09-30 07:58:50 +00:00
atomic-cmpxchg-flag.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
atomic-cmpxchg.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
atomic-fence.ll
atomic-load-store.ll [RISCV] Add codegen support for RV64A 2019-01-17 10:04:39 +00:00
atomic-rmw.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
bare-select.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
blockaddress.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
branch-relaxation.ll [RISCV] Match GNU tools canonical JALR and add aliases 2019-07-16 04:56:43 +00:00
branch.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
bswap-ctlz-cttz-ctpop.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
byval.ll
callee-saved-fpr32s.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
callee-saved-fpr64s.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
callee-saved-gprs.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-ilp32-ilp32f-common.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-ilp32.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-ilp32d.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-ilp32f-ilp32d-common.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-lp64-lp64f-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-lp64-lp64f-lp64d-common.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-lp64.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-rv32f-ilp32.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-sext-zext.ll
calls.ll [RISCV] Lower calls through PLT 2019-06-18 14:29:45 +00:00
codemodel-lowering.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
compress-inline-asm.ll [RISCV] Support llvm-objdump -M no-aliases and -M numeric 2019-09-10 16:24:03 +00:00
compress.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
disable-tail-calls.ll
div.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-arith.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-bitmanip-dagcombines.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-br-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-calling-conv.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-convert.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-frem.ll
double-imm.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-intrinsics.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-mem.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-previous-failure.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-select-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-stack-spill-restore.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
dwarf-eh.ll [RISCV][NFC] Remove outdated TODO from test/CodeGen/RISCV/dwarf-eh.ll 2019-07-17 14:04:48 +00:00
exception-pointer-register.ll [RISCV] Specify registers used in DWARF exception handling 2019-07-08 09:16:47 +00:00
fastcc-float.ll [RISCV] Support fast calling convention 2019-10-15 02:04:29 +00:00
fastcc-int.ll [RISCV] Support fast calling convention 2019-10-15 02:04:29 +00:00
fixups-diff.ll
fixups-relax-diff.ll [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame. 2019-07-19 02:03:34 +00:00
float-arith.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-bit-preserving-dagcombines.ll [RISCV] Support Bit-Preserving FP in F/D Extensions 2019-06-07 12:20:14 +00:00
float-bitmanip-dagcombines.ll [RISCV] Add RV64F codegen support 2019-01-31 22:48:38 +00:00
float-br-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-convert.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-frem.ll
float-imm.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-intrinsics.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-mem.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-select-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
flt-rounds.ll
fp128.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
frame-info.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
frame.ll Replace "no-frame-pointer-*" function attributes with "frame-pointer" 2019-01-14 10:55:55 +00:00
frameaddr-returnaddr.ll
get-setcc-result-type.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
hoist-global-addr-base.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
i32-icmp.ll [RISCV] Improve codegen for icmp {ne,eq} with a constant 2019-03-26 12:55:00 +00:00
imm-cse.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
imm.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
indirectbr.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
init-array.ll [IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format 2019-05-15 02:35:32 +00:00
inline-asm-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-clobbers.ll [RISCV] Add support for lowering floating point inlineasm clobbers 2019-07-31 09:07:21 +00:00
inline-asm-d-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-d-constraint-f.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
inline-asm-f-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-f-constraint-f.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
inline-asm-i-constraint-i1.ll [TargetLowering] Extend bool args to inline-asm according to getBooleanType 2019-05-22 16:16:15 +00:00
inline-asm-invalid.ll Emit diagnostic if an inline asm constraint requires an immediate 2019-08-03 05:52:47 +00:00
inline-asm.ll [RISCV] Fix a couple of tests' CHECKs 2019-08-30 12:11:47 +00:00
interrupt-attr-args-error.ll
interrupt-attr-invalid.ll
interrupt-attr-nocall.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
interrupt-attr-ret-error.ll
interrupt-attr.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
jumptable.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
large-stack.ll [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 2019-10-04 02:00:57 +00:00
legalize-fneg.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
lit.local.cfg
lsr-legaladdimm.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
mattr-invalid-combination.ll [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
mem.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
mem64.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
mul.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
musttail-call.ll
option-norelax.ll
option-norvc.ll [RISCV] Support llvm-objdump -M no-aliases and -M numeric 2019-09-10 16:24:03 +00:00
option-relax.ll
option-rvc.ll [RISCV] Support llvm-objdump -M no-aliases and -M numeric 2019-09-10 16:24:03 +00:00
pic-models.ll [RISCV] Add lowering of addressing sequences for PIC 2019-06-11 12:57:47 +00:00
pr40333.ll [RISCV] Custom-legalise 32-bit variable shifts on RV64 2019-01-25 05:04:00 +00:00
prefetch.ll
readcyclecounter.ll [RISCV] Support @llvm.readcyclecounter() Intrinsic 2019-07-05 12:35:21 +00:00
rem.ll [RISCV] Introduce codegen patterns for RV64M-only instructions 2019-01-12 07:43:06 +00:00
remat.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
rotl-rotr.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
rv32e.ll [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
rv32i-rv64i-float-double.ll [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall 2019-08-28 23:40:37 +00:00
rv64-large-stack.ll [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 2019-10-04 02:00:57 +00:00
rv64d-double-convert.ll [RISCV] Implement RV64D codegen 2019-02-01 03:53:30 +00:00
rv64f-float-convert.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
rv64i-complex-float.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
rv64i-exhaustive-w-insts.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
rv64i-single-softfloat.ll [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall 2019-08-28 23:40:37 +00:00
rv64i-tricky-shifts.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
rv64i-w-insts-legalization.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
rv64m-exhaustive-w-insts.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
rv64m-w-insts-legalization.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
sdata-limit-0.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-limit-4.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-limit-8.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-local-sym.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
select-cc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
select-optimize-multiple.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
select-optimize-multiple.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
setcc-logic.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
sext-zext-trunc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
shift-masked-shamt.ll
shifts.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
split-offsets.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
split-sp-adjust.ll [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 2019-10-04 02:00:57 +00:00
srem-lkk.ll [SelectionDAG] Add tests for LKK algorithm 2019-10-05 14:29:25 +00:00
srem-vector-lkk.ll [SelectionDAG] Add tests for LKK algorithm 2019-10-05 14:29:25 +00:00
stack-realignment-unsupported.ll [RISCV] Minimal stack realignment support 2019-08-08 14:40:54 +00:00
stack-realignment.ll [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 2019-10-04 02:00:57 +00:00
tail-calls.ll [RISCV] Enable tail call opt for variadic function 2019-09-04 02:03:36 +00:00
target-abi-invalid.ll [RISCV] Support -target-abi at the MC layer and for codegen 2019-03-09 09:28:06 +00:00
target-abi-valid.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
tls-models.ll [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
umulo-128-legalisation-lowering.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
urem-lkk.ll [SelectionDAG] Add tests for LKK algorithm 2019-10-05 14:29:25 +00:00
urem-vector-lkk.ll [SelectionDAG] Add tests for LKK algorithm 2019-10-05 14:29:25 +00:00
vararg.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
wide-mem.ll
zext-with-load-is-free.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00