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AsmParser
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[AMDGPU] Assembler: rework parsing of optional operands.
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2016-05-24 12:38:33 +00:00 |
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Disassembler
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Fix build warning introduced in r270552 "[AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers."
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2016-05-26 15:52:16 +00:00 |
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InstPrinter
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AMDGPU: Add support for MCExpr to instruction printer
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2016-05-13 20:39:24 +00:00 |
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MCTargetDesc
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AMDGPU: Fix incorrect simm check
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2016-05-18 19:07:58 +00:00 |
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TargetInfo
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Remove autoconf support
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2016-01-26 21:29:08 +00:00 |
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Utils
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AMDGPU: Fix getIntegerAttribute type and error message
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2016-05-12 02:45:18 +00:00 |
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AMDGPU.h
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AMDGPU/EG,CM: Add instruction to read from constant AS (VTX2)
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2016-05-13 20:39:16 +00:00 |
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AMDGPU.td
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[AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs
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2016-05-24 18:37:18 +00:00 |
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AMDGPUAlwaysInlinePass.cpp
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Cloning: Clean up the interface to the CloneFunction function.
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2016-05-10 20:23:24 +00:00 |
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AMDGPUAnnotateKernelFeatures.cpp
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AMDGPU: Implement addrspacecast
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2016-04-25 19:27:24 +00:00 |
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AMDGPUAnnotateUniformValues.cpp
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Add optimization bisect opt-in calls for AMDGPU passes
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2016-04-25 22:23:44 +00:00 |
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AMDGPUAsmPrinter.cpp
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[AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs
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2016-05-24 18:37:18 +00:00 |
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AMDGPUAsmPrinter.h
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[AMDGPU] Move reserved vgpr count for trap handler usage to SIMachineFunctionInfo + minor commenting changes
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2016-04-26 17:24:40 +00:00 |
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AMDGPUCallLowering.cpp
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AMDGPU: Add skeleton GlobalIsel implementation
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2016-04-14 19:09:28 +00:00 |
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AMDGPUCallLowering.h
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AMDGPU: Add skeleton GlobalIsel implementation
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2016-04-14 19:09:28 +00:00 |
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AMDGPUCallingConv.td
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AMDGPU: Add a shader calling convention
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2016-04-06 19:40:20 +00:00 |
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AMDGPUFrameLowering.cpp
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AMDGPU: Fix old comments that mention AMDIL
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2016-01-20 21:22:21 +00:00 |
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AMDGPUFrameLowering.h
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AMDGPU: Create emergency stack slots during frame lowering
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2015-11-06 18:17:45 +00:00 |
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AMDGPUISelDAGToDAG.cpp
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AMDGPU/R600: Implement memory loads from constant AS
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2016-05-13 20:39:29 +00:00 |
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AMDGPUISelLowering.cpp
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AMDGPU: Fix inconsistent lowering of select of vectors
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2016-05-25 17:34:58 +00:00 |
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AMDGPUISelLowering.h
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AMDGPU: Remove custom load/store scalarization
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2016-04-14 23:31:26 +00:00 |
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AMDGPUInstrInfo.cpp
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AMDGPU: Move subtarget specific code out of AMDGPUInstrInfo.cpp
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2016-01-28 16:04:37 +00:00 |
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AMDGPUInstrInfo.h
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AMDGPU: Add SIWholeQuadMode pass
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2016-03-21 20:28:33 +00:00 |
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AMDGPUInstrInfo.td
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AMDGPU: Make CONST_DATA_PTR available to R600
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2016-05-13 20:39:18 +00:00 |
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AMDGPUInstructions.td
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AMDGPU: Implement canonicalize
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2016-04-14 01:42:16 +00:00 |
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AMDGPUIntrinsicInfo.cpp
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[llvm-tblgen] Avoid StringMatcher for GCC and MS builtin names
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2016-01-27 01:43:12 +00:00 |
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AMDGPUIntrinsicInfo.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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AMDGPUIntrinsics.td
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AMDGPU: Remove bfi and bfm intrinsics
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2016-02-08 19:06:01 +00:00 |
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AMDGPUMCInstLower.cpp
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AMDGPU: Verify instructions in non-debug builds as well
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2016-03-16 09:10:42 +00:00 |
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AMDGPUMCInstLower.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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AMDGPUMachineFunction.cpp
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Revert "AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2."
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2016-05-06 14:59:04 +00:00 |
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AMDGPUMachineFunction.h
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Revert "AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2."
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2016-05-06 14:59:04 +00:00 |
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AMDGPUOpenCLImageTypeLoweringPass.cpp
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[NFC] Header cleanup
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2016-04-18 09:17:29 +00:00 |
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AMDGPUPromoteAlloca.cpp
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AMDGPU: Fix promote alloca for pointer loads
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2016-05-18 23:20:24 +00:00 |
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AMDGPURegisterInfo.cpp
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…
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AMDGPURegisterInfo.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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AMDGPURegisterInfo.td
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AMDGPU: Set SubRegIndex size and offset
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2015-07-30 17:03:11 +00:00 |
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AMDGPUSubtarget.cpp
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[AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs
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2016-05-24 18:37:18 +00:00 |
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AMDGPUSubtarget.h
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[AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs
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2016-05-24 18:37:18 +00:00 |
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AMDGPUTargetMachine.cpp
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Delete Reloc::Default.
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2016-05-18 22:04:49 +00:00 |
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AMDGPUTargetMachine.h
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Delete Reloc::Default.
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2016-05-18 22:04:49 +00:00 |
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AMDGPUTargetObjectFile.cpp
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AMDGPU/SI: Add support for AMD code object version 2.
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2016-05-05 17:03:33 +00:00 |
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AMDGPUTargetObjectFile.h
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AMDGPU/SI: Add support for AMD code object version 2.
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2016-05-05 17:03:33 +00:00 |
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AMDGPUTargetTransformInfo.cpp
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AMDGPU: llvm.SI.fs.constant is a source of divergence
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2016-05-02 17:37:01 +00:00 |
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AMDGPUTargetTransformInfo.h
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AMDGPU: Other sizes of popcnt are fast
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2016-05-18 16:10:19 +00:00 |
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AMDILCFGStructurizer.cpp
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Bug 20810: Use report_fatal_error instead of unreachable
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2016-03-02 03:33:55 +00:00 |
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AMDKernelCodeT.h
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[AMDGPU] fix amd_kernel_code_t bit field position as per spec (added missing reserved fields)
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2016-02-24 10:54:25 +00:00 |
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CIInstructions.td
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AMDGPU: Implement i64 global atomics
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2016-04-12 14:05:11 +00:00 |
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CMakeLists.txt
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[AMDGPU][NFC] Rename SIInsertNops -> SIDebuggerInsertNops
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2016-05-10 18:33:41 +00:00 |
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CaymanInstructions.td
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AMDGPU/EG,CM: Add instruction to read from constant AS (VTX2)
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2016-05-13 20:39:16 +00:00 |
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EvergreenInstructions.td
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AMDGPU/EG,CM: Add instruction to read from constant AS (VTX2)
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2016-05-13 20:39:16 +00:00 |
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GCNHazardRecognizer.cpp
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Silence unused variable warning; NFC.
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2016-05-03 15:17:25 +00:00 |
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GCNHazardRecognizer.h
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AMDGPU/SI: Use the hazard recognizer to break SMEM soft clauses
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2016-05-02 17:39:06 +00:00 |
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LLVMBuild.txt
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[AMDGPU] Disassembler: Added basic disassembler for AMDGPU target
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2016-02-18 03:42:32 +00:00 |
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Processors.td
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AMDGPU/SI: Add Polaris support
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2016-03-24 15:31:05 +00:00 |
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R600ClauseMergePass.cpp
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Add optimization bisect opt-in calls for AMDGPU passes
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2016-04-25 22:23:44 +00:00 |
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R600ControlFlowFinalizer.cpp
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AMDGPU/R600: Implement memory loads from constant AS
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2016-05-13 20:39:29 +00:00 |
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R600Defines.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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R600EmitClauseMarkers.cpp
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…
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R600ExpandSpecialInstrs.cpp
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…
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R600ISelLowering.cpp
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AMDGPU: Cleanup lowering actions
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2016-05-21 02:27:49 +00:00 |
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R600ISelLowering.h
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Fix instance of -Winconsistent-missing-override in AMDGPU code
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2016-05-02 19:45:10 +00:00 |
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R600InstrFormats.td
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…
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R600InstrInfo.cpp
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AMDGPU/R600: There are other uses for ALU_LITERAL besides Imm
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2016-05-13 20:39:20 +00:00 |
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R600InstrInfo.h
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[NFC] Header cleanup
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2016-04-18 09:17:29 +00:00 |
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R600Instructions.td
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AMDGPU/R600: Implement memory loads from constant AS
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2016-05-13 20:39:29 +00:00 |
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R600Intrinsics.td
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AMDGPU: Move AMDGPU intrinsics only used by R600
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2016-01-26 04:49:24 +00:00 |
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R600MachineFunctionInfo.cpp
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…
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R600MachineFunctionInfo.h
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[NFC] Header cleanup
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2016-04-18 09:17:29 +00:00 |
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R600MachineScheduler.cpp
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…
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R600MachineScheduler.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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R600OptimizeVectorRegisters.cpp
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Add optimization bisect opt-in calls for AMDGPU passes
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2016-04-25 22:23:44 +00:00 |
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R600Packetizer.cpp
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AMDGPU: Simplify boolean conditional return statements
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2016-03-02 23:00:21 +00:00 |
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R600RegisterInfo.cpp
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…
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R600RegisterInfo.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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R600RegisterInfo.td
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…
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R600Schedule.td
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…
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R600TextureIntrinsicsReplacer.cpp
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AMDGPU: Rename some r600 intrinsics to use correct TargetPrefix
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2016-01-22 19:00:09 +00:00 |
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R700Instructions.td
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…
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SIAnnotateControlFlow.cpp
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[StructurizeCFG] Annotate branches that were treated as uniform
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2016-04-14 17:42:35 +00:00 |
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SIDebuggerInsertNops.cpp
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[AMDGPU] Update nop insertion for debugger usage
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2016-05-13 18:21:28 +00:00 |
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SIDefines.h
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[AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers.
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2016-05-24 12:05:16 +00:00 |
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SIFixControlFlowLiveIntervals.cpp
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AMDGPU: Remove unused includes
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2015-09-25 00:28:43 +00:00 |
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SIFixSGPRCopies.cpp
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AMDGPU: Fix debug name of pass to better match
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2016-04-21 18:21:54 +00:00 |
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SIFoldOperands.cpp
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Add optimization bisect opt-in calls for AMDGPU passes
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2016-04-25 22:23:44 +00:00 |
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SIFrameLowering.cpp
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Soften assertion in AMDGPU emitPrologue.
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2016-05-25 01:45:42 +00:00 |
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SIFrameLowering.h
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AMDGPU: Remove SIPrepareScratchRegs
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2015-11-30 21:15:53 +00:00 |
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SIISelLowering.cpp
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[AMDGPU] Remove exit-on-error flag from test (PR27762)
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2016-05-26 15:24:55 +00:00 |
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SIISelLowering.h
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AMDGPU: Unify LowerGlobalAddress
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2016-05-13 20:39:34 +00:00 |
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SIInsertWaits.cpp
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AMDGPU/SI: Use the hazard recognizer to break SMEM soft clauses
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2016-05-02 17:39:06 +00:00 |
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SIInstrFormats.td
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[TableGen] AsmMatcher: support for default values for optional operands
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2016-05-06 11:31:17 +00:00 |
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SIInstrInfo.cpp
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AMDGPU: Fix verifier error when spilling SGPRs
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2016-05-21 00:53:42 +00:00 |
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SIInstrInfo.h
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AMDGPU: Handle cbranch vccz/vccnz
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2016-05-21 00:29:40 +00:00 |
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SIInstrInfo.td
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[AMDGPU] Assembler: rework parsing of optional operands.
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2016-05-24 12:38:33 +00:00 |
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SIInstructions.td
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AMDGPU: Fix v2i64/v2f64 bitcasts
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2016-05-25 18:07:36 +00:00 |
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SIIntrinsics.td
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Split IntrReadArgMem into IntrReadMem and IntrArgMemOnly
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2016-04-21 17:48:02 +00:00 |
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SILoadStoreOptimizer.cpp
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Add optimization bisect opt-in calls for AMDGPU passes
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2016-04-25 22:23:44 +00:00 |
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SILowerControlFlow.cpp
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AMDGPU: Also look for s_cbranch_vccz
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2016-05-19 18:20:25 +00:00 |
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SILowerI1Copies.cpp
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AMDGPU: Fix passes depending on dominator tree for no reason
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2016-02-11 06:15:34 +00:00 |
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SIMachineFunctionInfo.cpp
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[AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs
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2016-05-24 18:37:18 +00:00 |
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SIMachineFunctionInfo.h
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[AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs
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2016-05-24 18:37:18 +00:00 |
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SIMachineScheduler.cpp
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AMDGPU/SI: Use range loops to simplify some code in the SI Scheduler
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2016-05-03 16:30:56 +00:00 |
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SIMachineScheduler.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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SIRegisterInfo.cpp
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[AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs
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2016-05-24 18:37:18 +00:00 |
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SIRegisterInfo.h
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AMDGPU/SI: Enable the post-ra scheduler
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2016-04-30 00:23:06 +00:00 |
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SIRegisterInfo.td
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AMDGPU: Define priorities for register classes
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2016-05-21 03:55:07 +00:00 |
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SISchedule.td
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AMDGPU/SI: Enable the post-ra scheduler
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2016-04-30 00:23:06 +00:00 |
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SIShrinkInstructions.cpp
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Add optimization bisect opt-in calls for AMDGPU passes
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2016-04-25 22:23:44 +00:00 |
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SITypeRewriter.cpp
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AMDGPU: Add a shader calling convention
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2016-04-06 19:40:20 +00:00 |
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SIWholeQuadMode.cpp
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AMDGPU/SI: add llvm.amdgcn.ps.live intrinsic
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2016-04-22 04:04:08 +00:00 |
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VIInstrFormats.td
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[TableGen] AsmMatcher: support for default values for optional operands
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2016-05-06 11:31:17 +00:00 |
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VIInstructions.td
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[AMDGPU] Assembler: change v_madmk operands to have same order as mad.
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2016-03-11 09:27:25 +00:00 |
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