forked from OSchip/llvm-project
279 lines
9.7 KiB
C++
279 lines
9.7 KiB
C++
//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides ARM specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMMCTargetDesc.h"
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#include "ARMMCAsmInfo.h"
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#include "ARMBaseInfo.h"
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#include "InstPrinter/ARMInstPrinter.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#define GET_REGINFO_MC_DESC
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#include "ARMGenRegisterInfo.inc"
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#define GET_INSTRINFO_MC_DESC
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#include "ARMGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "ARMGenSubtargetInfo.inc"
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using namespace llvm;
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std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
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// Set the boolean corresponding to the current target triple, or the default
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// if one cannot be determined, to true.
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unsigned Len = TT.size();
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unsigned Idx = 0;
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// FIXME: Enhance Triple helper class to extract ARM version.
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bool isThumb = false;
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if (Len >= 5 && TT.substr(0, 4) == "armv")
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Idx = 4;
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else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
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isThumb = true;
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if (Len >= 7 && TT[5] == 'v')
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Idx = 6;
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}
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bool NoCPU = CPU == "generic" || CPU.empty();
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std::string ARMArchFeature;
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if (Idx) {
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unsigned SubVer = TT[Idx];
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if (SubVer >= '7' && SubVer <= '9') {
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if (Len >= Idx+2 && TT[Idx+1] == 'm') {
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if (NoCPU)
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// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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} else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
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if (NoCPU)
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// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
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// FeatureT2XtPk, FeatureMClass
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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} else {
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// v7 CPUs have lots of different feature sets. If no CPU is specified,
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// then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
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// the "minimum" feature set and use CPU string to figure out the exact
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// features.
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if (NoCPU)
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// v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
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ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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}
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} else if (SubVer == '6') {
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
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ARMArchFeature = "+v6t2";
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else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
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if (NoCPU)
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// v6m: FeatureNoARM, FeatureMClass
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ARMArchFeature = "+v6,+noarm,+mclass";
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else
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ARMArchFeature = "+v6";
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} else
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ARMArchFeature = "+v6";
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} else if (SubVer == '5') {
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
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ARMArchFeature = "+v5te";
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else
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ARMArchFeature = "+v5t";
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} else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
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ARMArchFeature = "+v4t";
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}
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if (isThumb) {
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if (ARMArchFeature.empty())
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ARMArchFeature = "+thumb-mode";
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else
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ARMArchFeature += ",+thumb-mode";
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}
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return ARMArchFeature;
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}
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MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS) {
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std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
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if (!FS.empty()) {
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if (!ArchFS.empty())
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ArchFS = ArchFS + "," + FS.str();
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else
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ArchFS = FS;
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}
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MCSubtargetInfo *X = new MCSubtargetInfo();
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InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
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return X;
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}
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static MCInstrInfo *createARMMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitARMMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitARMMCRegisterInfo(X, ARM::LR);
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return X;
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}
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static MCAsmInfo *createARMMCAsmInfo(const Target &T, StringRef TT) {
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Triple TheTriple(TT);
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if (TheTriple.isOSDarwin())
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return new ARMMCAsmInfoDarwin();
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return new ARMELFMCAsmInfo();
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}
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static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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if (RM == Reloc::Default) {
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Triple TheTriple(TT);
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// Default relocation model on Darwin is PIC, not DynamicNoPIC.
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RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
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}
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X->InitMCCodeGenInfo(RM, CM, OL);
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return X;
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}
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// This is duplicated code. Refactor this.
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static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
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MCContext &Ctx, MCAsmBackend &MAB,
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raw_ostream &OS,
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MCCodeEmitter *Emitter,
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bool RelaxAll,
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bool NoExecStack) {
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Triple TheTriple(TT);
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if (TheTriple.isOSDarwin())
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return createMachOStreamer(Ctx, MAB, OS, Emitter, false);
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if (TheTriple.isOSWindows()) {
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llvm_unreachable("ARM does not support Windows COFF format");
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}
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return createELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack);
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}
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static MCInstPrinter *createARMMCInstPrinter(const Target &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI) {
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if (SyntaxVariant == 0)
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return new ARMInstPrinter(MAI, MII, MRI, STI);
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return 0;
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}
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namespace {
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class ARMMCInstrAnalysis : public MCInstrAnalysis {
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public:
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ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
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virtual bool isUnconditionalBranch(const MCInst &Inst) const {
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// BCCs with the "always" predicate are unconditional branches.
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if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
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return true;
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return MCInstrAnalysis::isUnconditionalBranch(Inst);
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}
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virtual bool isConditionalBranch(const MCInst &Inst) const {
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// BCCs with the "always" predicate are unconditional branches.
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if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
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return false;
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return MCInstrAnalysis::isConditionalBranch(Inst);
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}
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uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
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uint64_t Size) const {
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// We only handle PCRel branches for now.
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if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
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return -1ULL;
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int64_t Imm = Inst.getOperand(0).getImm();
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// FIXME: This is not right for thumb.
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return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
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}
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};
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}
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static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
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return new ARMMCInstrAnalysis(Info);
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}
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// Force static initialization.
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extern "C" void LLVMInitializeARMTargetMC() {
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// Register the MC asm info.
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RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
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RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
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// Register the MC codegen info.
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TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
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TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
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TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
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ARM_MC::createARMMCSubtargetInfo);
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TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
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ARM_MC::createARMMCSubtargetInfo);
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// Register the MC instruction analyzer.
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TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
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createARMMCInstrAnalysis);
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TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
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createARMMCInstrAnalysis);
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// Register the MC Code Emitter
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TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
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TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
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// Register the asm backend.
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TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
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TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
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// Register the object streamer.
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TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
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TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
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TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
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}
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