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llvm-project/llvm/test/MC/Disassembler/AMDGPU
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Artem Tamazov 54bfd548aa [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions. 
Fixes Bug 30808.
Note that passing subtarget information to predicates seems too complicated, so gfx8-specific def smrd_offset_20 introduced.
Old gfx6/7-specific def renamed to smrd_offset_8 for clarity.
Lit tests updated.

Differential Revision: https://reviews.llvm.org/D26085

llvm-svn: 285590
 		2016-10-31 16:07:39 +00:00
..
dpp_vi.txt [AMDGPU] Disassembler: support for DPP 2016-03-31 14:15:04 +00:00
ds_vi.txt [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed. 2016-10-21 14:49:22 +00:00
flat_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
lit.local.cfg
…
missing_op.txt [AMDGPU] fix failure on printing of non-existing instruction operands. 2016-08-15 10:56:48 +00:00
mov.txt
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mubuf_vi.txt [AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3. 2016-10-07 15:53:16 +00:00
nop.txt
…
sdwa_vi.txt [AMDGPU] Disassembler: Support for sdwa instructions 2016-06-09 11:04:45 +00:00
smem_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
smrd_vi.txt [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions. 2016-10-31 16:07:39 +00:00
sop1_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
sop2_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
sopc_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
sopk_vi.txt [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers. 2016-04-27 15:17:03 +00:00
sopp_vi.txt [AMDGPU][llvm-mc] Add support for sendmsg(...) syntax. 2016-05-06 17:48:48 +00:00
trap_vi.txt [AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers. 2016-05-24 12:05:16 +00:00
vop1.txt
…
vop1_vi.txt [AMDGPU] Add some VI disassembler tests missing from previous autogeneration due to different filecheck prefix. NFC. 2016-04-08 05:42:20 +00:00
vop2_vi.txt [AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC. 2016-06-06 15:23:43 +00:00
vop3_vi.txt [AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC. 2016-06-06 15:23:43 +00:00
vopc_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00