llvm-project/llvm/test/Transforms/LoopVectorize/PowerPC
Wei Mi 79997a24d7 Recommit the patch "Use uniforms set to populate VecValuesToIgnore".
For instructions in uniform set, they will not have vector versions so
add them to VecValuesToIgnore.
For induction vars, those only used in uniform instructions or consecutive
ptrs instructions have already been added to VecValuesToIgnore above. For
those induction vars which are only used in uniform instructions or
non-consecutive/non-gather scatter ptr instructions, the related phi and
update will also be added into VecValuesToIgnore set.

The change will make the vector RegUsages estimation less conservative.

Differential Revision: https://reviews.llvm.org/D20474

The recommit fixed the testcase global_alias.ll.

llvm-svn: 275936
2016-07-19 00:50:43 +00:00
..
agg-interleave-a2.ll
large-loop-rdx.ll Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT. 2016-02-26 19:40:34 +00:00
lit.local.cfg
small-loop-rdx.ll Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT. 2016-02-26 19:40:34 +00:00
stride-vectorization.ll [LV] Fix PR26600: avoid out of bounds loads for interleaved access vectorization 2016-02-19 15:46:10 +00:00
vectorize-only-for-real.ll [LoopVectorize] Don't vectorize loops when everything will be scalarized 2016-03-30 19:37:08 +00:00
vsx-tsvc-s173.ll Recommit the patch "Use uniforms set to populate VecValuesToIgnore". 2016-07-19 00:50:43 +00:00