forked from OSchip/llvm-project
d3dc31009f
Refactor how . instructions are handled. In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.
For example, instead of this:
-def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "and. $rA, $rS, $rB">;
We now have this:
+def AND : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and $rA, $rS, $rB">;
llvm-svn: 21225
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| .. | ||
| Alpha | ||
| CBackend | ||
| IA64 | ||
| PowerPC | ||
| Skeleton | ||
| SparcV8 | ||
| SparcV9 | ||
| X86 | ||
| MRegisterInfo.cpp | ||
| Makefile | ||
| Target.td | ||
| TargetData.cpp | ||
| TargetFrameInfo.cpp | ||
| TargetInstrInfo.cpp | ||
| TargetLowering.cpp | ||
| TargetMachine.cpp | ||
| TargetMachineRegistry.cpp | ||
| TargetSchedInfo.cpp | ||