forked from OSchip/llvm-project
70 lines
2.3 KiB
LLVM
70 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc < %s -mtriple=armv6-unknown-linux-gnu | FileCheck %s --check-prefixes=ARMV6
|
|
; RUN: llc < %s -mtriple=armv7-unknown-linux-gnu | FileCheck %s --check-prefixes=ARMV7
|
|
|
|
define { i64, i8 } @mulodi_test(i64 %l, i64 %r) unnamed_addr #0 {
|
|
; ARMV6-LABEL: mulodi_test:
|
|
; ARMV6: @ %bb.0: @ %start
|
|
; ARMV6-NEXT: push {r4, r5, r6, lr}
|
|
; ARMV6-NEXT: umull r12, lr, r3, r0
|
|
; ARMV6-NEXT: mov r6, #0
|
|
; ARMV6-NEXT: umull r4, r5, r1, r2
|
|
; ARMV6-NEXT: umull r0, r2, r0, r2
|
|
; ARMV6-NEXT: add r4, r4, r12
|
|
; ARMV6-NEXT: adds r12, r2, r4
|
|
; ARMV6-NEXT: adc r2, r6, #0
|
|
; ARMV6-NEXT: cmp r3, #0
|
|
; ARMV6-NEXT: movne r3, #1
|
|
; ARMV6-NEXT: cmp r1, #0
|
|
; ARMV6-NEXT: movne r1, #1
|
|
; ARMV6-NEXT: cmp r5, #0
|
|
; ARMV6-NEXT: and r1, r1, r3
|
|
; ARMV6-NEXT: movne r5, #1
|
|
; ARMV6-NEXT: cmp lr, #0
|
|
; ARMV6-NEXT: orr r1, r1, r5
|
|
; ARMV6-NEXT: movne lr, #1
|
|
; ARMV6-NEXT: orr r1, r1, lr
|
|
; ARMV6-NEXT: orr r2, r1, r2
|
|
; ARMV6-NEXT: mov r1, r12
|
|
; ARMV6-NEXT: pop {r4, r5, r6, pc}
|
|
;
|
|
; ARMV7-LABEL: mulodi_test:
|
|
; ARMV7: @ %bb.0: @ %start
|
|
; ARMV7-NEXT: push {r4, r5, r11, lr}
|
|
; ARMV7-NEXT: umull r12, lr, r1, r2
|
|
; ARMV7-NEXT: cmp r3, #0
|
|
; ARMV7-NEXT: umull r4, r5, r3, r0
|
|
; ARMV7-NEXT: movwne r3, #1
|
|
; ARMV7-NEXT: cmp r1, #0
|
|
; ARMV7-NEXT: movwne r1, #1
|
|
; ARMV7-NEXT: umull r0, r2, r0, r2
|
|
; ARMV7-NEXT: cmp lr, #0
|
|
; ARMV7-NEXT: and r1, r1, r3
|
|
; ARMV7-NEXT: movwne lr, #1
|
|
; ARMV7-NEXT: cmp r5, #0
|
|
; ARMV7-NEXT: orr r1, r1, lr
|
|
; ARMV7-NEXT: movwne r5, #1
|
|
; ARMV7-NEXT: orr r3, r1, r5
|
|
; ARMV7-NEXT: add r1, r12, r4
|
|
; ARMV7-NEXT: mov r5, #0
|
|
; ARMV7-NEXT: adds r1, r2, r1
|
|
; ARMV7-NEXT: adc r2, r5, #0
|
|
; ARMV7-NEXT: orr r2, r3, r2
|
|
; ARMV7-NEXT: pop {r4, r5, r11, pc}
|
|
start:
|
|
%0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %l, i64 %r) #2
|
|
%1 = extractvalue { i64, i1 } %0, 0
|
|
%2 = extractvalue { i64, i1 } %0, 1
|
|
%3 = zext i1 %2 to i8
|
|
%4 = insertvalue { i64, i8 } undef, i64 %1, 0
|
|
%5 = insertvalue { i64, i8 } %4, i8 %3, 1
|
|
ret { i64, i8 } %5
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone speculatable
|
|
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #1
|
|
|
|
attributes #0 = { nounwind readnone uwtable }
|
|
attributes #1 = { nounwind readnone speculatable }
|
|
attributes #2 = { nounwind }
|