llvm-project

History

Francis Visoiu Mistrih 8b2ab91a5d [DebugInfo][X86] Add start-after flags to MIR tests These tests would fail with -verify-machineinstrs because the MI generated from the IR would be merged with the one already in the MIR files, and we get the following error: ``` * Bad machine code: Function has NoVRegs property but there are VReg operands * - function: f ``` Differential Revision: https://reviews.llvm.org/D49191 llvm-svn: 336907		2018-07-12 14:36:48 +00:00
..
AArch64	[NFC] MIR-Canon: switching to a stable string sorting of instructions.	2018-05-13 06:07:20 +00:00
AMDGPU	[MIR-Canon] Fixing a test failure caused by COPY Folding.	2018-04-16 09:31:49 +00:00
ARM	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
Generic	[MIRParser] Add parser support for 'true' and 'false' i1s.	2018-06-05 00:17:13 +00:00
Hexagon	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
Mips	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
NVPTX	[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.	2018-01-10 00:56:48 +00:00
PowerPC	[if-converter] Handle BBs that terminate in ret during diamond conversion	2018-04-19 17:26:46 +00:00
WebAssembly	[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)	2018-05-08 02:02:50 +00:00
X86	[DebugInfo][X86] Add start-after flags to MIR tests	2018-07-12 14:36:48 +00:00
README	Add README describing the intention of test/CodeGen/MIR	2016-12-09 20:16:12 +00:00

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.