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AArch64
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[GlobalISel] Fix equality for copies from physregs in matchEqualDefs
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2020-03-27 17:52:21 -07:00 |
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AMDGPU
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[AMDGPU] Fix getEUsPerCU for gfx10 in CU mode
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2020-03-27 20:36:49 +00:00 |
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ARC
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…
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ARM
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[ARM] Move ConstantIsland and LowOverheadLoops Passes.
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2020-03-25 16:49:21 +01:00 |
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AVR
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[AVR] Fix incorrect register state for LDRdPtr
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2020-03-03 17:34:54 +08:00 |
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BPF
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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Generic
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[X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG.
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2020-03-26 14:10:20 -07:00 |
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Hexagon
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Revert "Include static prof data when collecting loop BBs"
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2020-03-24 09:41:16 -07:00 |
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Inputs
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…
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Lanai
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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MIR
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[AMDGPU] Move frame pointer from s34 to s33
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2020-03-19 15:35:16 -04:00 |
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MSP430
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…
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Mips
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[GlobalISel] combine G_TRUNC with G_MERGE_VALUES
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2020-03-16 14:42:01 +01:00 |
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NVPTX
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CodeGen: Add -denormal-fp-math-f32 flag
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2020-03-27 14:00:39 -07:00 |
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PowerPC
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[FEnv] Constfold some unary constrained operations
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2020-03-28 12:28:33 +07:00 |
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RISCV
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[RISCV] Support llvm.thread.pointer
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2020-03-27 17:30:12 -07:00 |
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SPARC
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[Sparc] Fix incorrect operand for matching CMPri pattern
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2020-03-02 11:36:32 +08:00 |
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SystemZ
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[SystemZ] Improve foldMemoryOperandImpl()
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2020-03-25 16:21:08 +01:00 |
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Thumb
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[DAGCombine] Skip PostInc combine with later users
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2020-03-23 08:39:53 +00:00 |
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Thumb2
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[ARM][LowOverheadLoops] DoubleWidthResult instructions canGenerateZeros
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2020-03-27 15:26:13 +00:00 |
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VE
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[VE] Target-specific bit size for sjljehprepare
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2020-03-10 17:51:16 +01:00 |
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WebAssembly
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[WebAssembly] Fix the order of destructors in the LowerGlobalDtors pass.
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2020-03-26 16:19:02 -07:00 |
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WinCFGuard
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…
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WinEH
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X86
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[X86][SSE] Add original PR38522 test case
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2020-03-28 10:56:57 +00:00 |
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XCore
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[XCore] Add instruction pattern for bitrev
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2020-02-21 09:28:49 +08:00 |
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