Jim Grosbach d343166a0b Many Thumb2 instructions can reference the full ARM register set (i.e., ... have 4 bits per register in the operand encoding), but have undefined behavior when the operand value is 13 or 15 (SP and PC, respectively). The trivial coalescer in linear scan sometimes will merge a copy from SP into a subsequent instruction which uses the copy, and if that instruction cannot legally reference SP, we get bad code such as: mls r0,r9,r0,sp instead of: mov r2, sp mls r0, r9, r0, r2 This patch adds a new register class for use by Thumb2 that excludes the problematic registers (SP and PC) and is used instead of GPR for those operands which cannot legally reference PC or SP. The trivial coalescer explicitly requires that the register class of the destination for the COPY instruction contain the source register for the COPY to be considered for coalescing. This prevents errant instructions like that above. PR7499 llvm-svn: 109842		2010-07-30 02:41:01 +00:00
clang	Add test case for crash reported in <rdar://problem/8236270> (which has since been fixed in trunk).	2010-07-30 01:10:48 +00:00
compiler-rt	add assembly implementation of modsi3 so compiler does not have to special case a - (a / b) * b optimization	2010-07-27 06:24:32 +00:00
libcxx	Make complex.h play nice with C	2010-07-29 18:43:15 +00:00
lldb	Add a test case to test that lldb command "command source" works correctly.	2010-07-29 21:42:28 +00:00
llvm	Many Thumb2 instructions can reference the full ARM register set (i.e.,	2010-07-30 02:41:01 +00:00