forked from OSchip/llvm-project
500 lines
16 KiB
C++
500 lines
16 KiB
C++
//===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains support for writing dwarf debug info into asm files.
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//
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//===----------------------------------------------------------------------===//
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#include "DwarfExpression.h"
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#include "DwarfCompileUnit.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/SmallBitVector.h"
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#include "llvm/BinaryFormat/Dwarf.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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void DwarfExpression::emitConstu(uint64_t Value) {
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if (Value < 32)
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emitOp(dwarf::DW_OP_lit0 + Value);
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else if (Value == std::numeric_limits<uint64_t>::max()) {
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// Only do this for 64-bit values as the DWARF expression stack uses
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// target-address-size values.
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emitOp(dwarf::DW_OP_lit0);
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emitOp(dwarf::DW_OP_not);
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} else {
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emitOp(dwarf::DW_OP_constu);
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emitUnsigned(Value);
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}
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}
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void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
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assert(DwarfReg >= 0 && "invalid negative dwarf register number");
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assert((LocationKind == Unknown || LocationKind == Register) &&
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"location description already locked down");
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LocationKind = Register;
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if (DwarfReg < 32) {
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emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
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} else {
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emitOp(dwarf::DW_OP_regx, Comment);
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emitUnsigned(DwarfReg);
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}
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}
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void DwarfExpression::addBReg(int DwarfReg, int Offset) {
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assert(DwarfReg >= 0 && "invalid negative dwarf register number");
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assert(LocationKind != Register && "location description already locked down");
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if (DwarfReg < 32) {
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emitOp(dwarf::DW_OP_breg0 + DwarfReg);
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} else {
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emitOp(dwarf::DW_OP_bregx);
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emitUnsigned(DwarfReg);
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}
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emitSigned(Offset);
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}
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void DwarfExpression::addFBReg(int Offset) {
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emitOp(dwarf::DW_OP_fbreg);
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emitSigned(Offset);
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}
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void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
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if (!SizeInBits)
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return;
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const unsigned SizeOfByte = 8;
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if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
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emitOp(dwarf::DW_OP_bit_piece);
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emitUnsigned(SizeInBits);
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emitUnsigned(OffsetInBits);
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} else {
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emitOp(dwarf::DW_OP_piece);
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unsigned ByteSize = SizeInBits / SizeOfByte;
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emitUnsigned(ByteSize);
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}
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this->OffsetInBits += SizeInBits;
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}
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void DwarfExpression::addShr(unsigned ShiftBy) {
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emitConstu(ShiftBy);
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emitOp(dwarf::DW_OP_shr);
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}
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void DwarfExpression::addAnd(unsigned Mask) {
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emitConstu(Mask);
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emitOp(dwarf::DW_OP_and);
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}
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bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
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unsigned MachineReg, unsigned MaxSize) {
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if (!TRI.isPhysicalRegister(MachineReg)) {
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if (isFrameRegister(TRI, MachineReg)) {
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DwarfRegs.push_back({-1, 0, nullptr});
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return true;
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}
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return false;
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}
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int Reg = TRI.getDwarfRegNum(MachineReg, false);
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// If this is a valid register number, emit it.
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if (Reg >= 0) {
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DwarfRegs.push_back({Reg, 0, nullptr});
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return true;
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}
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// Walk up the super-register chain until we find a valid number.
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// For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
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for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
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Reg = TRI.getDwarfRegNum(*SR, false);
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if (Reg >= 0) {
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unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
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unsigned Size = TRI.getSubRegIdxSize(Idx);
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unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
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DwarfRegs.push_back({Reg, 0, "super-register"});
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// Use a DW_OP_bit_piece to describe the sub-register.
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setSubRegisterPiece(Size, RegOffset);
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return true;
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}
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}
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// Otherwise, attempt to find a covering set of sub-register numbers.
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// For example, Q0 on ARM is a composition of D0+D1.
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unsigned CurPos = 0;
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// The size of the register in bits.
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const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
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unsigned RegSize = TRI.getRegSizeInBits(*RC);
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// Keep track of the bits in the register we already emitted, so we
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// can avoid emitting redundant aliasing subregs. Because this is
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// just doing a greedy scan of all subregisters, it is possible that
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// this doesn't find a combination of subregisters that fully cover
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// the register (even though one may exist).
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SmallBitVector Coverage(RegSize, false);
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for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
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unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
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unsigned Size = TRI.getSubRegIdxSize(Idx);
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unsigned Offset = TRI.getSubRegIdxOffset(Idx);
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Reg = TRI.getDwarfRegNum(*SR, false);
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if (Reg < 0)
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continue;
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// Intersection between the bits we already emitted and the bits
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// covered by this subregister.
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SmallBitVector CurSubReg(RegSize, false);
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CurSubReg.set(Offset, Offset + Size);
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// If this sub-register has a DWARF number and we haven't covered
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// its range, emit a DWARF piece for it.
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if (CurSubReg.test(Coverage)) {
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// Emit a piece for any gap in the coverage.
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if (Offset > CurPos)
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DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"});
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DwarfRegs.push_back(
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{Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
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if (Offset >= MaxSize)
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break;
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// Mark it as emitted.
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Coverage.set(Offset, Offset + Size);
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CurPos = Offset + Size;
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}
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}
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// Failed to find any DWARF encoding.
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if (CurPos == 0)
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return false;
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// Found a partial or complete DWARF encoding.
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if (CurPos < RegSize)
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DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
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return true;
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}
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void DwarfExpression::addStackValue() {
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if (DwarfVersion >= 4)
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emitOp(dwarf::DW_OP_stack_value);
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}
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void DwarfExpression::addSignedConstant(int64_t Value) {
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assert(LocationKind == Implicit || LocationKind == Unknown);
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LocationKind = Implicit;
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emitOp(dwarf::DW_OP_consts);
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emitSigned(Value);
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}
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void DwarfExpression::addUnsignedConstant(uint64_t Value) {
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assert(LocationKind == Implicit || LocationKind == Unknown);
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LocationKind = Implicit;
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emitConstu(Value);
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}
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void DwarfExpression::addUnsignedConstant(const APInt &Value) {
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assert(LocationKind == Implicit || LocationKind == Unknown);
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LocationKind = Implicit;
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unsigned Size = Value.getBitWidth();
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const uint64_t *Data = Value.getRawData();
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// Chop it up into 64-bit pieces, because that's the maximum that
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// addUnsignedConstant takes.
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unsigned Offset = 0;
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while (Offset < Size) {
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addUnsignedConstant(*Data++);
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if (Offset == 0 && Size <= 64)
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break;
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addStackValue();
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addOpPiece(std::min(Size - Offset, 64u), Offset);
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Offset += 64;
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}
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}
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bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
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DIExpressionCursor &ExprCursor,
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unsigned MachineReg,
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unsigned FragmentOffsetInBits) {
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auto Fragment = ExprCursor.getFragmentInfo();
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if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
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LocationKind = Unknown;
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return false;
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}
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bool HasComplexExpression = false;
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auto Op = ExprCursor.peek();
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if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
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HasComplexExpression = true;
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// If the register can only be described by a complex expression (i.e.,
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// multiple subregisters) it doesn't safely compose with another complex
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// expression. For example, it is not possible to apply a DW_OP_deref
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// operation to multiple DW_OP_pieces.
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if (HasComplexExpression && DwarfRegs.size() > 1) {
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DwarfRegs.clear();
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LocationKind = Unknown;
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return false;
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}
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// Handle simple register locations.
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if (LocationKind != Memory && !HasComplexExpression) {
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for (auto &Reg : DwarfRegs) {
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if (Reg.DwarfRegNo >= 0)
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addReg(Reg.DwarfRegNo, Reg.Comment);
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addOpPiece(Reg.Size);
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}
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DwarfRegs.clear();
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return true;
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}
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// Don't emit locations that cannot be expressed without DW_OP_stack_value.
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if (DwarfVersion < 4)
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if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
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return Op.getOp() == dwarf::DW_OP_stack_value;
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})) {
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DwarfRegs.clear();
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LocationKind = Unknown;
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return false;
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}
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assert(DwarfRegs.size() == 1);
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auto Reg = DwarfRegs[0];
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bool FBReg = isFrameRegister(TRI, MachineReg);
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int SignedOffset = 0;
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assert(Reg.Size == 0 && "subregister has same size as superregister");
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// Pattern-match combinations for which more efficient representations exist.
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// [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
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if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
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SignedOffset = Op->getArg(0);
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ExprCursor.take();
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}
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// [Reg, DW_OP_constu, Offset, DW_OP_plus] --> [DW_OP_breg, Offset]
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// [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
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// If Reg is a subregister we need to mask it out before subtracting.
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if (Op && Op->getOp() == dwarf::DW_OP_constu) {
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auto N = ExprCursor.peekNext();
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if (N && (N->getOp() == dwarf::DW_OP_plus ||
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(N->getOp() == dwarf::DW_OP_minus && !SubRegisterSizeInBits))) {
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int Offset = Op->getArg(0);
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SignedOffset = (N->getOp() == dwarf::DW_OP_minus) ? -Offset : Offset;
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ExprCursor.consume(2);
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}
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}
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if (FBReg)
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addFBReg(SignedOffset);
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else
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addBReg(Reg.DwarfRegNo, SignedOffset);
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DwarfRegs.clear();
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return true;
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}
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/// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
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static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
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while (ExprCursor) {
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auto Op = ExprCursor.take();
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switch (Op->getOp()) {
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case dwarf::DW_OP_deref:
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case dwarf::DW_OP_LLVM_fragment:
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break;
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default:
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return false;
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}
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}
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return true;
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}
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void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
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unsigned FragmentOffsetInBits) {
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// If we need to mask out a subregister, do it now, unless the next
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// operation would emit an OpPiece anyway.
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auto N = ExprCursor.peek();
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if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
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maskSubRegister();
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Optional<DIExpression::ExprOperand> PrevConvertOp = None;
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while (ExprCursor) {
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auto Op = ExprCursor.take();
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switch (Op->getOp()) {
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case dwarf::DW_OP_LLVM_fragment: {
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unsigned SizeInBits = Op->getArg(1);
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unsigned FragmentOffset = Op->getArg(0);
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// The fragment offset must have already been adjusted by emitting an
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// empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
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// location.
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assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
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// If addMachineReg already emitted DW_OP_piece operations to represent
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// a super-register by splicing together sub-registers, subtract the size
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// of the pieces that was already emitted.
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SizeInBits -= OffsetInBits - FragmentOffset;
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// If addMachineReg requested a DW_OP_bit_piece to stencil out a
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// sub-register that is smaller than the current fragment's size, use it.
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if (SubRegisterSizeInBits)
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SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
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// Emit a DW_OP_stack_value for implicit location descriptions.
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if (LocationKind == Implicit)
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addStackValue();
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// Emit the DW_OP_piece.
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addOpPiece(SizeInBits, SubRegisterOffsetInBits);
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setSubRegisterPiece(0, 0);
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// Reset the location description kind.
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LocationKind = Unknown;
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return;
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}
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case dwarf::DW_OP_plus_uconst:
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assert(LocationKind != Register);
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emitOp(dwarf::DW_OP_plus_uconst);
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emitUnsigned(Op->getArg(0));
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break;
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case dwarf::DW_OP_plus:
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case dwarf::DW_OP_minus:
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case dwarf::DW_OP_mul:
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case dwarf::DW_OP_div:
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case dwarf::DW_OP_mod:
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case dwarf::DW_OP_or:
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case dwarf::DW_OP_and:
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case dwarf::DW_OP_xor:
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case dwarf::DW_OP_shl:
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case dwarf::DW_OP_shr:
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case dwarf::DW_OP_shra:
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case dwarf::DW_OP_lit0:
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case dwarf::DW_OP_not:
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case dwarf::DW_OP_dup:
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emitOp(Op->getOp());
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break;
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case dwarf::DW_OP_deref:
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assert(LocationKind != Register);
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if (LocationKind != Memory && ::isMemoryLocation(ExprCursor))
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// Turning this into a memory location description makes the deref
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// implicit.
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LocationKind = Memory;
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else
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emitOp(dwarf::DW_OP_deref);
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break;
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case dwarf::DW_OP_constu:
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assert(LocationKind != Register);
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emitConstu(Op->getArg(0));
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break;
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case dwarf::DW_OP_LLVM_convert: {
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unsigned BitSize = Op->getArg(0);
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dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
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if (DwarfVersion >= 5) {
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emitOp(dwarf::DW_OP_convert);
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// Reuse the base_type if we already have one in this CU otherwise we
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// create a new one.
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unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
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for (; I != E; ++I)
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if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
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CU.ExprRefedBaseTypes[I].Encoding == Encoding)
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break;
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if (I == E)
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CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
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// If targeting a location-list; simply emit the index into the raw
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// byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
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// fitted with means to extract it later.
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// If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
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// (containing the index and a resolve mechanism during emit) into the
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// DIE value list.
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emitBaseTypeRef(I);
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} else {
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if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
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if (Encoding == dwarf::DW_ATE_signed)
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emitLegacySExt(PrevConvertOp->getArg(0));
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else if (Encoding == dwarf::DW_ATE_unsigned)
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emitLegacyZExt(PrevConvertOp->getArg(0));
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PrevConvertOp = None;
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} else {
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PrevConvertOp = Op;
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}
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}
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break;
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}
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case dwarf::DW_OP_stack_value:
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LocationKind = Implicit;
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break;
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case dwarf::DW_OP_swap:
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assert(LocationKind != Register);
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emitOp(dwarf::DW_OP_swap);
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break;
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case dwarf::DW_OP_xderef:
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assert(LocationKind != Register);
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emitOp(dwarf::DW_OP_xderef);
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break;
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default:
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llvm_unreachable("unhandled opcode found in expression");
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}
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}
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if (LocationKind == Implicit)
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// Turn this into an implicit location description.
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addStackValue();
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}
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/// add masking operations to stencil out a subregister.
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void DwarfExpression::maskSubRegister() {
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assert(SubRegisterSizeInBits && "no subregister was registered");
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if (SubRegisterOffsetInBits > 0)
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addShr(SubRegisterOffsetInBits);
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uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
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addAnd(Mask);
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}
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void DwarfExpression::finalize() {
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assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
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// Emit any outstanding DW_OP_piece operations to mask out subregisters.
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if (SubRegisterSizeInBits == 0)
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return;
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// Don't emit a DW_OP_piece for a subregister at offset 0.
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if (SubRegisterOffsetInBits == 0)
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return;
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addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
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}
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void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
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if (!Expr || !Expr->isFragment())
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return;
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uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
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assert(FragmentOffset >= OffsetInBits &&
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"overlapping or duplicate fragments");
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if (FragmentOffset > OffsetInBits)
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addOpPiece(FragmentOffset - OffsetInBits);
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OffsetInBits = FragmentOffset;
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}
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void DwarfExpression::emitLegacySExt(unsigned FromBits) {
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// (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
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emitOp(dwarf::DW_OP_dup);
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emitOp(dwarf::DW_OP_constu);
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emitUnsigned(FromBits - 1);
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emitOp(dwarf::DW_OP_shr);
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emitOp(dwarf::DW_OP_lit0);
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emitOp(dwarf::DW_OP_not);
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emitOp(dwarf::DW_OP_mul);
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emitOp(dwarf::DW_OP_constu);
|
|
emitUnsigned(FromBits);
|
|
emitOp(dwarf::DW_OP_shl);
|
|
emitOp(dwarf::DW_OP_or);
|
|
}
|
|
|
|
void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
|
|
// (X & (1 << FromBits - 1))
|
|
emitOp(dwarf::DW_OP_constu);
|
|
emitUnsigned((1ULL << FromBits) - 1);
|
|
emitOp(dwarf::DW_OP_and);
|
|
}
|