forked from OSchip/llvm-project
35 lines
1.3 KiB
LLVM
35 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s
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define weak_odr amdgpu_kernel void @test_mul24_knownbits_kernel(float addrspace(1)* %p) #4 {
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; GCN-LABEL: test_mul24_knownbits_kernel:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_and_b32_e32 v0, 3, v0
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; GCN-NEXT: v_mul_i32_i24_e32 v0, 0xfffffb, v0
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; GCN-NEXT: v_and_b32_e32 v0, 0xffffffe0, v0
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; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; GCN-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v2, s1
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; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
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; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc
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; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: global_store_dword v[0:1], v2, off
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; GCN-NEXT: s_endpgm
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entry:
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%0 = tail call i32 @llvm.amdgcn.workitem.id.x() #28, !range !4
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%tid = and i32 %0, 3
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%1 = mul nsw i32 %tid, -5
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%v1 = and i32 %1, -32
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%v2 = sext i32 %v1 to i64
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%v3 = getelementptr inbounds float, float addrspace(1)* %p, i64 %v2
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store float 0.000, float addrspace(1)* %v3, align 4
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ret void
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}
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; Function Attrs: nounwind readnone speculatable
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declare i32 @llvm.amdgcn.workitem.id.x() #20
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!4 = !{i32 0, i32 1024}
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