forked from OSchip/llvm-project
242 lines
6.4 KiB
LLVM
242 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IM %s
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define i32 @udiv(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: udiv:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: lui a2, %hi(__udivsi3)
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; RV32I-NEXT: addi a2, a2, %lo(__udivsi3)
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; RV32I-NEXT: jalr a2
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: udiv:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: divu a0, a0, a1
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; RV32IM-NEXT: ret
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%1 = udiv i32 %a, %b
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ret i32 %1
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}
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define i32 @udiv_constant(i32 %a) nounwind {
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; RV32I-LABEL: udiv_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: lui a1, %hi(__udivsi3)
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; RV32I-NEXT: addi a2, a1, %lo(__udivsi3)
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; RV32I-NEXT: addi a1, zero, 5
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; RV32I-NEXT: jalr a2
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: udiv_constant:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a1, 838861
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; RV32IM-NEXT: addi a1, a1, -819
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; RV32IM-NEXT: mulhu a0, a0, a1
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; RV32IM-NEXT: srli a0, a0, 2
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; RV32IM-NEXT: ret
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%1 = udiv i32 %a, 5
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ret i32 %1
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}
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define i32 @udiv_pow2(i32 %a) nounwind {
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; RV32I-LABEL: udiv_pow2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srli a0, a0, 3
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: udiv_pow2:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: srli a0, a0, 3
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; RV32IM-NEXT: ret
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%1 = udiv i32 %a, 8
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ret i32 %1
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}
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define i64 @udiv64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: udiv64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: lui a4, %hi(__udivdi3)
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; RV32I-NEXT: addi a4, a4, %lo(__udivdi3)
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; RV32I-NEXT: jalr a4
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: udiv64:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi sp, sp, -16
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; RV32IM-NEXT: sw ra, 12(sp)
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; RV32IM-NEXT: lui a4, %hi(__udivdi3)
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; RV32IM-NEXT: addi a4, a4, %lo(__udivdi3)
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; RV32IM-NEXT: jalr a4
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; RV32IM-NEXT: lw ra, 12(sp)
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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%1 = udiv i64 %a, %b
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ret i64 %1
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}
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define i64 @udiv64_constant(i64 %a) nounwind {
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; RV32I-LABEL: udiv64_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: lui a2, %hi(__udivdi3)
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; RV32I-NEXT: addi a4, a2, %lo(__udivdi3)
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; RV32I-NEXT: addi a2, zero, 5
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; RV32I-NEXT: mv a3, zero
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; RV32I-NEXT: jalr a4
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: udiv64_constant:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi sp, sp, -16
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; RV32IM-NEXT: sw ra, 12(sp)
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; RV32IM-NEXT: lui a2, %hi(__udivdi3)
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; RV32IM-NEXT: addi a4, a2, %lo(__udivdi3)
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; RV32IM-NEXT: addi a2, zero, 5
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; RV32IM-NEXT: mv a3, zero
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; RV32IM-NEXT: jalr a4
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; RV32IM-NEXT: lw ra, 12(sp)
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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%1 = udiv i64 %a, 5
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ret i64 %1
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}
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define i32 @sdiv(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sdiv:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: lui a2, %hi(__divsi3)
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; RV32I-NEXT: addi a2, a2, %lo(__divsi3)
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; RV32I-NEXT: jalr a2
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: sdiv:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: div a0, a0, a1
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; RV32IM-NEXT: ret
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%1 = sdiv i32 %a, %b
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ret i32 %1
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}
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define i32 @sdiv_constant(i32 %a) nounwind {
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; RV32I-LABEL: sdiv_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: lui a1, %hi(__divsi3)
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; RV32I-NEXT: addi a2, a1, %lo(__divsi3)
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; RV32I-NEXT: addi a1, zero, 5
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; RV32I-NEXT: jalr a2
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: sdiv_constant:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a1, 419430
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; RV32IM-NEXT: addi a1, a1, 1639
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; RV32IM-NEXT: mulh a0, a0, a1
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; RV32IM-NEXT: srli a1, a0, 31
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; RV32IM-NEXT: srai a0, a0, 1
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: ret
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%1 = sdiv i32 %a, 5
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ret i32 %1
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}
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define i32 @sdiv_pow2(i32 %a) nounwind {
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; RV32I-LABEL: sdiv_pow2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a1, a0, 31
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; RV32I-NEXT: srli a1, a1, 29
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: srai a0, a0, 3
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: sdiv_pow2:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: srai a1, a0, 31
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; RV32IM-NEXT: srli a1, a1, 29
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: srai a0, a0, 3
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; RV32IM-NEXT: ret
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%1 = sdiv i32 %a, 8
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ret i32 %1
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}
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define i64 @sdiv64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: sdiv64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: lui a4, %hi(__divdi3)
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; RV32I-NEXT: addi a4, a4, %lo(__divdi3)
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; RV32I-NEXT: jalr a4
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: sdiv64:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi sp, sp, -16
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; RV32IM-NEXT: sw ra, 12(sp)
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; RV32IM-NEXT: lui a4, %hi(__divdi3)
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; RV32IM-NEXT: addi a4, a4, %lo(__divdi3)
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; RV32IM-NEXT: jalr a4
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; RV32IM-NEXT: lw ra, 12(sp)
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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%1 = sdiv i64 %a, %b
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ret i64 %1
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}
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define i64 @sdiv64_constant(i64 %a) nounwind {
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; RV32I-LABEL: sdiv64_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: lui a2, %hi(__divdi3)
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; RV32I-NEXT: addi a4, a2, %lo(__divdi3)
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; RV32I-NEXT: addi a2, zero, 5
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; RV32I-NEXT: mv a3, zero
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; RV32I-NEXT: jalr a4
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: sdiv64_constant:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi sp, sp, -16
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; RV32IM-NEXT: sw ra, 12(sp)
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; RV32IM-NEXT: lui a2, %hi(__divdi3)
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; RV32IM-NEXT: addi a4, a2, %lo(__divdi3)
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; RV32IM-NEXT: addi a2, zero, 5
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; RV32IM-NEXT: mv a3, zero
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; RV32IM-NEXT: jalr a4
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; RV32IM-NEXT: lw ra, 12(sp)
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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%1 = sdiv i64 %a, 5
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ret i64 %1
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}
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