llvm-project

History

Francis Visoiu Mistrih e4718e84e8 [MIR] Add support for addrspace in MIR Add support for printing / parsing the addrspace of a MachineMemOperand. Fixes PR35970. Differential Revision: https://reviews.llvm.org/D42502 llvm-svn: 323521		2018-01-26 11:47:28 +00:00
..
AArch64	[MIR] Add support for addrspace in MIR	2018-01-26 11:47:28 +00:00
AMDGPU	[MIR] Add support for addrspace in MIR	2018-01-26 11:47:28 +00:00
ARM	Move tests to the correct place	2018-01-19 06:08:15 +00:00
Generic	[RegAllocFast] Add the proper initialize method to use the .mir infrastructure	2017-07-07 19:25:42 +00:00
Hexagon	[Hexagon] Handle Hexagon-specific machine operand target flags in MIR	2017-07-10 18:31:02 +00:00
Mips	[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.	2018-01-10 00:56:48 +00:00
NVPTX	[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.	2018-01-10 00:56:48 +00:00
PowerPC	MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.	2016-08-24 01:32:41 +00:00
X86	[x86] Mostly reautogenerate a bunch of tests that affect D37775. NFC	2018-01-23 15:48:50 +00:00
README	Add README describing the intention of test/CodeGen/MIR	2016-12-09 20:16:12 +00:00

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.