forked from OSchip/llvm-project
27 lines
693 B
LLVM
27 lines
693 B
LLVM
; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
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; CHECK: memw
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; Check that the testcase compiles without errors.
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target triple = "hexagon"
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; Function Attrs: nounwind
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define i32 @f0(i32* %a0, i32 %a1) #0 {
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b0:
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br label %b1
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b1: ; preds = %b0
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%v0 = load i32, i32* %a0, align 4
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%v1 = mul nsw i32 2, %v0
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%v2 = icmp slt i32 %a1, %v1
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br i1 %v2, label %b2, label %b3
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b2: ; preds = %b1
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ret i32 0
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b3: ; preds = %b1
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ret i32 %v1
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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