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llvm-project/llvm/test/CodeGen/MIR
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Diogo Sampaio 8232497c31 [ARM][THUMB2] Allow emitting T3 types of add and sub 
Summary:
This patch allows to emit thumb2 add and sub
instructions with 12 bit immediates in the
emitT2RegPlusImmediate function.
- Splitting parts of the D70680

Reviewers: eli.friedman, olista01, efriedma

Reviewed By: efriedma

Subscribers: efriedma, kristof.beyls, hiraditya, dmgreen, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71361
 		2019-12-30 11:03:58 +00:00
..
AArch64 [MIRNamer]: Make the check lines in the test robust with regex. 2019-11-16 22:58:45 -08:00
AMDGPU [llvm][MIRVRegNamerUtils] Adding hashing on memoperands. 2019-12-11 22:11:49 -05:00
ARM [ARM][THUMB2] Allow emitting T3 types of add and sub 2019-12-30 11:03:58 +00:00
Generic [llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands. 2019-12-16 18:25:04 -05:00
Hexagon [DebugInfo] Allow bundled calls in the MIR's call site info 2019-08-19 12:41:22 +00:00
Mips [MIParser] Set RegClassOrRegBank during instruction parsing 2019-10-22 14:25:37 +00:00
NVPTX
…
PowerPC [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC 2019-09-13 14:18:36 +00:00
WebAssembly [WebAssembly] Fix tests missed in rL374235 2019-10-09 23:06:38 +00:00
X86 Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351 2019-12-24 16:27:51 -08:00
README
…

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.