forked from OSchip/llvm-project
391 lines
15 KiB
YAML
391 lines
15 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: test_min_max_ValK0_K1_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_min_max_ValK0_K1_i32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY2]], [[COPY3]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK-NEXT: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 -12
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_SMAX %0, %7
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%4:sgpr(s32) = G_CONSTANT i32 17
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_SMIN %3, %8
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: min_max_ValK0_K1_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: min_max_ValK0_K1_i32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY2]], [[COPY3]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK-NEXT: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 -12
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_SMAX %7, %0
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%4:sgpr(s32) = G_CONSTANT i32 17
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_SMIN %3, %8
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_min_K1max_ValK0__i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_min_K1max_ValK0__i32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY2]], [[COPY3]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK-NEXT: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 -12
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_SMAX %0, %7
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%4:sgpr(s32) = G_CONSTANT i32 17
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_SMIN %8, %3
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_min_K1max_K0Val__i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_min_K1max_K0Val__i32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY2]], [[COPY3]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK-NEXT: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 -12
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_SMAX %7, %0
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%4:sgpr(s32) = G_CONSTANT i32 17
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_SMIN %8, %3
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_max_min_ValK1_K0_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_max_min_ValK1_K0_i32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY3]], [[COPY2]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK-NEXT: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 17
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_SMIN %0, %7
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%4:sgpr(s32) = G_CONSTANT i32 -12
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_SMAX %3, %8
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_max_min_K1Val_K0_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_max_min_K1Val_K0_i32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY3]], [[COPY2]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK-NEXT: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 17
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_SMIN %7, %0
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%4:sgpr(s32) = G_CONSTANT i32 -12
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_SMAX %3, %8
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_max_K0min_ValK1__i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_max_K0min_ValK1__i32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY3]], [[COPY2]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK-NEXT: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 17
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_SMIN %0, %7
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%4:sgpr(s32) = G_CONSTANT i32 -12
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_SMAX %8, %3
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_max_K0min_K1Val__i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_max_K0min_K1Val__i32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY3]], [[COPY2]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK-NEXT: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 17
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_SMIN %7, %0
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%4:sgpr(s32) = G_CONSTANT i32 -12
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_SMAX %8, %3
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_max_K0min_K1Val__v2i16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_max_K0min_K1Val__v2i16
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
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; CHECK-NEXT: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
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; CHECK-NEXT: [[SMIN:%[0-9]+]]:vgpr(<2 x s16>) = G_SMIN [[COPY2]], [[COPY]]
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
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; CHECK-NEXT: [[SMAX:%[0-9]+]]:vgpr(<2 x s16>) = G_SMAX [[COPY3]], [[SMIN]]
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; CHECK-NEXT: $vgpr0 = COPY [[SMAX]](<2 x s16>)
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK-NEXT: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%9:sgpr(s32) = G_CONSTANT i32 17
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%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %9(s32), %9(s32)
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%10:sgpr(s32) = G_CONSTANT i32 -12
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%5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %10(s32), %10(s32)
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%11:vgpr(<2 x s16>) = COPY %2(<2 x s16>)
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|
%4:vgpr(<2 x s16>) = G_SMIN %11, %0
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|
%12:vgpr(<2 x s16>) = COPY %5(<2 x s16>)
|
|
%7:vgpr(<2 x s16>) = G_SMAX %12, %4
|
|
$vgpr0 = COPY %7(<2 x s16>)
|
|
%8:ccr_sgpr_64 = COPY %1
|
|
S_SETPC_B64_return %8, implicit $vgpr0
|
|
...
|
|
|
|
---
|
|
name: test_uniform_min_max
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $sgpr2
|
|
|
|
; CHECK-LABEL: name: test_uniform_min_max
|
|
; CHECK: liveins: $sgpr2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
|
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
|
|
; CHECK-NEXT: [[SMAX:%[0-9]+]]:sgpr(s32) = G_SMAX [[COPY]], [[C]]
|
|
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
|
|
; CHECK-NEXT: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[SMAX]], [[C1]]
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[SMIN]](s32)
|
|
; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
|
|
; CHECK-NEXT: $sgpr0 = COPY [[INT]](s32)
|
|
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
|
|
%0:sgpr(s32) = COPY $sgpr2
|
|
%3:sgpr(s32) = G_CONSTANT i32 -12
|
|
%4:sgpr(s32) = G_SMAX %0, %3
|
|
%5:sgpr(s32) = G_CONSTANT i32 17
|
|
%6:sgpr(s32) = G_SMIN %4, %5
|
|
%8:vgpr(s32) = COPY %6(s32)
|
|
%7:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), %8(s32)
|
|
$sgpr0 = COPY %7(s32)
|
|
SI_RETURN_TO_EPILOG implicit $sgpr0
|
|
...
|
|
|
|
---
|
|
name: test_non_inline_constant_i32
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $vgpr0, $sgpr30_sgpr31
|
|
|
|
; CHECK-LABEL: name: test_non_inline_constant_i32
|
|
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
|
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
|
|
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
|
|
; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY2]], [[COPY3]]
|
|
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
|
|
; CHECK-NEXT: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
|
|
; CHECK-NEXT: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%1:sgpr_64 = COPY $sgpr30_sgpr31
|
|
%2:sgpr(s32) = G_CONSTANT i32 -12
|
|
%7:vgpr(s32) = COPY %2(s32)
|
|
%3:vgpr(s32) = G_SMAX %0, %7
|
|
%4:sgpr(s32) = G_CONSTANT i32 65
|
|
%8:vgpr(s32) = COPY %4(s32)
|
|
%5:vgpr(s32) = G_SMIN %3, %8
|
|
$vgpr0 = COPY %5(s32)
|
|
%6:ccr_sgpr_64 = COPY %1
|
|
S_SETPC_B64_return %6, implicit $vgpr0
|
|
...
|