Amara Emerson 6cdfe29d8e [GlobalISel][IRTranslator] Use RPO traversal when visiting blocks to translate. ... Previously we were just visiting the blocks in the function in IR order, which is rather arbitrary. Therefore we wouldn't always visit defs before uses, but the translation code relies on this assumption in some places. Only codegen change seen in tests is an elision of a redundant copy. Fixes PR38396 llvm-svn: 338476		2018-08-01 02:17:42 +00:00
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AArch64	[GlobalISel][IRTranslator] Use RPO traversal when visiting blocks to translate.	2018-08-01 02:17:42 +00:00
AMDGPU	AMDGPU: Add clamp bit to dot intrinsics	2018-08-01 01:31:30 +00:00
ARC	…
ARM	Revert r338354 "[ARM] Revert r337821"	2018-07-31 23:09:42 +00:00
AVR	[AVR] Set trackLivenessAfterRegAlloc	2018-06-11 14:46:48 +00:00
BPF	bpf: add missing RegState to notify MachineInstr verifier necessary register usage	2018-07-27 16:58:52 +00:00
Generic	Implement strip.invariant.group	2018-07-02 04:49:30 +00:00
Hexagon	[Hexagon] Simplify A4_rcmp[n]eqi R, 0	2018-07-30 14:28:02 +00:00
Inputs	…
Lanai	…
MIR	[DebugInfo][X86] Add start-after flags to MIR tests	2018-07-12 14:36:48 +00:00
MSP430	…
Mips	[DAGCombiner] Teach DAG combiner that A-(B-C) can be folded to A+(C-B)	2018-07-28 00:27:25 +00:00
NVPTX	finish: [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests	2018-07-11 20:31:51 +00:00
Nios2	…
PowerPC	[DAGCombiner] transform sub-of-shifted-signbit to add	2018-07-30 22:21:37 +00:00
RISCV	[RISCV] Fixed test case failure due to r338047	2018-07-31 00:36:28 +00:00
SPARC	Regenerate remainder test.	2018-07-20 13:14:29 +00:00
SystemZ	[SystemZ] Improve decoding in case of instructions with four register operands.	2018-07-31 13:00:42 +00:00
Thumb	[ARM] Prefer lsls+lsrs over lsls+ands or lsrs+ands in Thumb1.	2018-07-25 18:22:22 +00:00
Thumb2	[ARM] Treat cmn immediates as legal in isLegalICmpImmediate.	2018-07-10 23:44:37 +00:00
WebAssembly	Revert "[WebAssembly] Added default stack-only instruction mode for MC."	2018-07-27 23:19:51 +00:00
WinCFGuard	…
WinEH	…
X86	[X86][SSE] Use ISD::MULHU for constant/non-zero ISD::SRL lowering (PR38151)	2018-07-31 18:05:56 +00:00
XCore	[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)	2018-07-15 16:27:07 +00:00