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llvm-project/llvm/lib/Target/RISCV
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Alex Bradbury 757d296222 [RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases 
As noted by Eli Friedman <https://reviews.llvm.org/D52977?id=168629#1315291>, 
the RV64I shift patterns for SLLW/SRLW/SRAW make some incorrect assumptions. 
SRAW assumed that (sext_inreg foo, i32) could only be produced when 
sign-extended an i32. However, it can be produced by input such as:

define i64 @tricky_ashr(i64 %a, i64 %b) {
  %1 = shl i64 %a, 32
  %2 = ashr i64 %1, 32
  %3 = ashr i64 %2, %b
  ret i64 %3
}

It's important not to select sraw in the above case, because sraw only uses 
bits lower 5 bits from the shift, while a shift of 32-63 would be valid.

Similarly, the patterns for srlw assumed (and foo, 0xffffffff) would only be 
produced when zero-extending a value that was originally i32 in LLVM IR. This
is obviously incorrect.

This patch removes the SLLW/SRLW/SRAW shift patterns for the time being and 
adds test cases that would demonstrate a miscompile if the incorrect patterns 
were re-added.

llvm-svn: 348067
 		2018-12-01 05:00:00 +00:00
..
AsmParser [RISCV] Support .option push and .option pop 2018-11-28 16:39:14 +00:00
Disassembler [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
InstPrinter [RISCV] Fix disassembling of fence instruction with invalid field 2018-10-11 22:49:13 +00:00
MCTargetDesc [RISCV] Support .option push and .option pop 2018-11-28 16:39:14 +00:00
TargetInfo
…
Utils [RISCV][NFC] Define and use the new CA instruction format 2018-11-16 10:33:23 +00:00
CMakeLists.txt [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
LLVMBuild.txt [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
RISCV.h [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
RISCV.td [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
RISCVAsmPrinter.cpp Revert "[RISCV] implement li pseudo instruction" 2018-04-18 19:02:31 +00:00
RISCVCallingConv.td [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
RISCVExpandPseudoInsts.cpp [RISCV] Implement codegen for cmpxchg on RV32IA 2018-11-29 20:43:42 +00:00
RISCVFrameLowering.cpp [RISCV] Fix std::advance slowness 2018-08-24 23:13:59 +00:00
RISCVFrameLowering.h [RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects 2018-03-20 01:39:17 +00:00
RISCVISelDAGToDAG.cpp [RISCV] Introduce codegen patterns for instructions introduced in RV64I 2018-11-30 09:38:44 +00:00
RISCVISelLowering.cpp [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V 2018-11-30 09:56:54 +00:00
RISCVISelLowering.h [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V 2018-11-30 09:56:54 +00:00
RISCVInstrFormats.td [RISCV][NFC] Define and use the new CA instruction format 2018-11-16 10:33:23 +00:00
RISCVInstrFormatsC.td [RISCV][NFC] Define and use the new CA instruction format 2018-11-16 10:33:23 +00:00
RISCVInstrInfo.cpp [RISCV] Remove overzealous is64Bit checks 2018-10-04 14:30:03 +00:00
RISCVInstrInfo.h [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot 2018-04-26 15:34:27 +00:00
RISCVInstrInfo.td [RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases 2018-12-01 05:00:00 +00:00
RISCVInstrInfoA.td [RISCV] Implement codegen for cmpxchg on RV32IA 2018-11-29 20:43:42 +00:00
RISCVInstrInfoC.td [RISCV] Add UNIMP instruction (32- and 16-bit forms) 2018-11-30 13:39:17 +00:00
RISCVInstrInfoD.td [RISCV] Gate float<->int and double<->int conversion patterns on IsRV32 2018-10-03 11:35:22 +00:00
RISCVInstrInfoF.td [RISCV] Gate float<->int and double<->int conversion patterns on IsRV32 2018-10-03 11:35:22 +00:00
RISCVInstrInfoM.td [RISCV] Codegen support for the standard RV32M instruction set extension 2018-01-18 12:36:38 +00:00
RISCVMCInstLower.cpp [RISCV] Add codegen for RV32F floating point load/store 2018-03-20 13:26:12 +00:00
RISCVMachineFunctionInfo.h [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv 2018-04-12 05:34:25 +00:00
RISCVMergeBaseOffset.cpp Test commit. 2018-08-02 05:38:18 +00:00
RISCVRegisterInfo.cpp [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
RISCVRegisterInfo.h [RISCV] Set isReMaterializable on ADDI and LUI instructions 2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.td [RISCV] Lower the tail pseudoinstruction 2018-05-23 22:44:08 +00:00
RISCVSubtarget.cpp
…
RISCVSubtarget.h [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation 2018-05-15 01:28:50 +00:00
RISCVSystemOperands.td [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
RISCVTargetMachine.cpp [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A 2018-09-19 10:54:22 +00:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp [RISCV] Use init_array instead of ctors for RISCV target, by default 2018-03-24 18:37:19 +00:00
RISCVTargetObjectFile.h [RISCV] Use init_array instead of ctors for RISCV target, by default 2018-03-24 18:37:19 +00:00