forked from OSchip/llvm-project
2efb59a719
The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] llvm-svn: 175164 |
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AArch64 | ||
ARM | ||
AsmParser | ||
COFF | ||
Disassembler | ||
ELF | ||
MBlaze | ||
MachO | ||
Markup | ||
Mips | ||
PowerPC | ||
X86 |