forked from OSchip/llvm-project
fc13bdd2db
Summary: Previously 0 and -1 was matched via tablegen rules. But this could cause problems where a physical register was being used where a virtual register was expected (seen in optimizeSelect and TwoAddressInstructionPass). Instead follow AArch64 and match in DAGToDAGISel. Reviewers: eliben, majnemer Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D27171 llvm-svn: 288215 |
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| .. | ||
| codemodel.ll | ||
| comparisons_i32.ll | ||
| comparisons_i64.ll | ||
| constant_multiply.ll | ||
| delay_filler.ll | ||
| i32.ll | ||
| lanai-misched-trivial-disjoint.ll | ||
| lit.local.cfg | ||
| mem_alu_combiner.ll | ||
| multiply.ll | ||
| rshift64.ll | ||
| select.ll | ||
| set_and_hi.ll | ||
| shift.ll | ||
| stack-frame.ll | ||
| sub-cmp-peephole.ll | ||
| subword.ll | ||