forked from OSchip/llvm-project
104 lines
5.0 KiB
YAML
104 lines
5.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -enable-unsafe-fp-math -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: fract_f64_neg
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: fract_f64_neg
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; CHECK: liveins: $sgpr0_sgpr1
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; CHECK: $vcc_hi = IMPLICIT_DEF
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; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 36, 0, 0 :: (dereferenceable invariant load 16, align 4, addrspace 4)
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; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
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; CHECK: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub2_sub3
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; CHECK: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY2]], 0, 0, 0 :: (load 8, addrspace 1)
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; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; CHECK: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
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; CHECK: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
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; CHECK: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]
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; CHECK: %12:vreg_64 = nofpexcept V_ADD_F64 0, [[COPY3]], 1, [[COPY4]], 0, 0, implicit $mode, implicit $exec
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; CHECK: %15:vreg_64 = nofpexcept V_FRACT_F64_e64 0, %12, 0, 0, implicit $mode, implicit $exec
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; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], %15, [[COPY1]], 0, 0, 0, 0, implicit $exec :: (store 8, addrspace 1)
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; CHECK: S_ENDPGM 0
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%2:sgpr(p4) = COPY $sgpr0_sgpr1
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%7:sgpr(s64) = G_CONSTANT i64 36
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%8:sgpr(p4) = G_PTR_ADD %2, %7(s64)
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%9:sgpr(<2 x s64>) = G_LOAD %8(p4) :: (dereferenceable invariant load 16, align 4, addrspace 4)
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%10:sgpr(s64) = G_EXTRACT %9(<2 x s64>), 0
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%13:sgpr(s64) = G_EXTRACT %9(<2 x s64>), 64
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%15:sgpr(p1) = G_INTTOPTR %13(s64)
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%18:sgpr(s64) = G_LOAD %15(p1) :: (load 8, addrspace 1)
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%19:sgpr(s64) = G_FCONSTANT double -0.000000e+00
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%24:sgpr(s64) = G_FNEG %18
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%25:vgpr(s64) = COPY %19(s64)
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%26:vgpr(s64) = COPY %24(s64)
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%20:vgpr(s64) = G_FADD %25, %26
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%21:vgpr(s64) = G_FFLOOR %20
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%23:vgpr(s64) = G_FNEG %21
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%22:vgpr(s64) = G_FADD %20, %23
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%12:sgpr(p1) = G_INTTOPTR %10(s64)
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%27:vgpr(p1) = COPY %12(p1)
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G_STORE %22(s64), %27(p1) :: (store 8, addrspace 1)
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S_ENDPGM 0
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...
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---
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name: fract_f64_neg_abs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: fract_f64_neg_abs
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; CHECK: liveins: $sgpr0_sgpr1
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; CHECK: $vcc_hi = IMPLICIT_DEF
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; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 36, 0, 0 :: (dereferenceable invariant load 16, align 4, addrspace 4)
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; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
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; CHECK: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub2_sub3
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; CHECK: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY2]], 0, 0, 0 :: (load 8, addrspace 1)
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; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; CHECK: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
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; CHECK: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
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; CHECK: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]
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; CHECK: %13:vreg_64 = nofpexcept V_ADD_F64 0, [[COPY3]], 3, [[COPY4]], 0, 0, implicit $mode, implicit $exec
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; CHECK: %16:vreg_64 = nofpexcept V_FRACT_F64_e64 0, %13, 0, 0, implicit $mode, implicit $exec
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; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], %16, [[COPY1]], 0, 0, 0, 0, implicit $exec :: (store 8, addrspace 1)
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; CHECK: S_ENDPGM 0
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%2:sgpr(p4) = COPY $sgpr0_sgpr1
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%7:sgpr(s64) = G_CONSTANT i64 36
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%8:sgpr(p4) = G_PTR_ADD %2, %7(s64)
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%9:sgpr(<2 x s64>) = G_LOAD %8(p4) :: (dereferenceable invariant load 16, align 4, addrspace 4)
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%10:sgpr(s64) = G_EXTRACT %9(<2 x s64>), 0
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%13:sgpr(s64) = G_EXTRACT %9(<2 x s64>), 64
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%15:sgpr(p1) = G_INTTOPTR %13(s64)
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%18:sgpr(s64) = G_LOAD %15(p1) :: (load 8, addrspace 1)
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%19:sgpr(s64) = G_FABS %18
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%20:sgpr(s64) = G_FCONSTANT double -0.000000e+00
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%25:sgpr(s64) = G_FNEG %19
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%26:vgpr(s64) = COPY %20(s64)
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%27:vgpr(s64) = COPY %25(s64)
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%21:vgpr(s64) = G_FADD %26, %27
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%22:vgpr(s64) = G_FFLOOR %21
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%24:vgpr(s64) = G_FNEG %22
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%23:vgpr(s64) = G_FADD %21, %24
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%12:sgpr(p1) = G_INTTOPTR %10(s64)
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%28:vgpr(p1) = COPY %12(p1)
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G_STORE %23(s64), %28(p1) :: (store 8, addrspace 1)
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S_ENDPGM 0
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...
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