llvm-project/llvm/test/MC/Disassembler
Stanislav Mekhanoshin 5cf8167735 [AMDGPU] gfx1010 allows VOP3 to have a literal
Differential Revision: https://reviews.llvm.org/D61413

llvm-svn: 359756
2019-05-02 04:01:39 +00:00
..
AArch64 [AArch64] Update v8.5a MTE LDG/STG instructions 2019-04-03 14:12:13 +00:00
AMDGPU [AMDGPU] gfx1010 allows VOP3 to have a literal 2019-05-02 04:01:39 +00:00
ARC [ARC] Add more load/store variants. 2019-03-14 20:50:54 +00:00
ARM ARM: disallow add/sub to sp unless Rn is also sp. 2019-04-23 13:50:13 +00:00
Hexagon NFC - Various typo fixes in tests 2018-07-04 13:28:39 +00:00
Lanai
MSP430 [MSP430] Minor fixes/improvements for assembler/disassembler 2019-01-10 22:59:50 +00:00
Mips Fixed typos in tests: s/CEHCK/CHECK/ 2019-02-25 13:12:33 +00:00
PowerPC [PowerPC] Fix reversed bit issue in DCMX mask for "xvtstdcdp" and "xvtstdcsp" P9 implementation 2019-04-02 16:56:01 +00:00
RISCV [RISCV] Fix test/MC/Disassembler/RISCV/invalid-instruction.txt after rL347988 2018-12-03 10:35:46 +00:00
Sparc [Sparc] Add membar assembler tags 2018-12-13 15:29:12 +00:00
SystemZ [SystemZ] Add support for IBM z14 processor (3/3) 2017-07-17 17:44:20 +00:00
WebAssembly [WebAssembly] Fixed disassembler not knowing about OPERAND_EVENT 2019-02-20 00:55:59 +00:00
X86 [X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two arguments where on is %st. 2019-02-04 17:28:18 +00:00
XCore