forked from OSchip/llvm-project
112 lines
4.4 KiB
LLVM
112 lines
4.4 KiB
LLVM
; RUN: opt %loadPolly -polly-allow-nonaffine -polly-scops -analyze < %s | FileCheck %s
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;
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; Verify only the incoming scalar x is modeled as a read in the non-affine
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; region.
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;
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; void f(int *A, int b) {
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; int x;
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; for (int i = 0; i < 1024; i++) {
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; if (b > i)
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; x = 0;
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; else if (b < 2 * i)
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; x = 3;
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; else
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; x = b;
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;
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; if (A[x])
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; A[x] = 0;
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; }
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; }
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;
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; TODO: We build a complicated representation of Stmt_bb10__TO__bb18's domain that will also complicate the schedule.
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; Once the domain is simple this test should fail and this TODO can be removed.
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; CHECK: Statements {
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; CHECK-NEXT: Stmt_bb3
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [b] -> { Stmt_bb3[i0] : 0 <= i0 <= 1023 and i0 < b };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [b] -> { Stmt_bb3[i0] -> [i0, 2] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [b] -> { Stmt_bb3[i0] -> MemRef_x_1__phi[] };
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; CHECK-NEXT: Stmt_bb7
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [b] -> { Stmt_bb7[i0] : i0 >= b and 0 <= i0 <= 1023 and 2i0 > b };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [b] -> { Stmt_bb7[i0] -> [i0, 1] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [b] -> { Stmt_bb7[i0] -> MemRef_x_1__phi[] };
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; CHECK-NEXT: Stmt_bb8
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [b] -> { Stmt_bb8[0] : b = 0 };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [b] -> { Stmt_bb8[i0] -> [0, 0] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [b] -> { Stmt_bb8[i0] -> MemRef_x_1__phi[] };
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; CHECK-NEXT: Stmt_bb10__TO__bb18
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [b] -> { Stmt_bb10__TO__bb18[i0] : 0 <= i0 <= 1023 and (i0 < b or (i0 >= b and 2i0 > b)); Stmt_bb10__TO__bb18[0] : b = 0 };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [b] -> { Stmt_bb10__TO__bb18[i0] -> [i0, 3] : i0 < b or (i0 >= b and 2i0 > b); Stmt_bb10__TO__bb18[0] -> [0, 3] : b = 0 };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [b] -> { Stmt_bb10__TO__bb18[i0] -> MemRef_x_1__phi[] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [b] -> { Stmt_bb10__TO__bb18[i0] -> MemRef_A[o0] : -2147483648 <= o0 <= 2147483647 };
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; CHECK-NEXT: MayWriteAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [b] -> { Stmt_bb10__TO__bb18[i0] -> MemRef_A[o0] : -2147483648 <= o0 <= 2147483647 };
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; CHECK-NEXT: }
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define void @f(i32* %A, i32 %b) {
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bb:
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br label %bb1
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bb1: ; preds = %bb19, %bb
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%i.0 = phi i32 [ 0, %bb ], [ %tmp20, %bb19 ]
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%exitcond = icmp ne i32 %i.0, 1024
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br i1 %exitcond, label %bb2, label %bb21
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bb2: ; preds = %bb1
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%tmp = icmp slt i32 %i.0, %b
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br i1 %tmp, label %bb3, label %bb4
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bb3: ; preds = %bb2
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br label %bb10
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bb4: ; preds = %bb2
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%tmp5 = mul nsw i32 %i.0, 2
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%tmp6 = icmp sgt i32 %tmp5, %b
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br i1 %tmp6, label %bb7, label %bb8
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bb7: ; preds = %bb4
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br label %bb10
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bb8: ; preds = %bb4
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br label %bb10
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bb10: ; preds = %bb9, %bb3
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%x.1 = phi i32 [ 0, %bb3 ], [ 3, %bb7 ], [ %b, %bb8 ]
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%tmp11 = sext i32 %x.1 to i64
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%tmp12 = getelementptr inbounds i32, i32* %A, i64 %tmp11
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%tmp13 = load i32, i32* %tmp12, align 4
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%tmp14 = icmp eq i32 %tmp13, 0
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br i1 %tmp14, label %bb18, label %bb15
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bb15: ; preds = %bb10
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%tmp16 = sext i32 %x.1 to i64
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%tmp17 = getelementptr inbounds i32, i32* %A, i64 %tmp16
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store i32 0, i32* %tmp17, align 4
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br label %bb18
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bb18: ; preds = %bb10, %bb15
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br label %bb19
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bb19: ; preds = %bb18
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%tmp20 = add nuw nsw i32 %i.0, 1
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br label %bb1
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bb21: ; preds = %bb1
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ret void
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}
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