forked from OSchip/llvm-project
244 lines
6.9 KiB
C++
244 lines
6.9 KiB
C++
//===-- HexagonMachineScheduler.h - Custom Hexagon MI scheduler. ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Custom Hexagon MI scheduler.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
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#include "llvm/ADT/PriorityQueue.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/CodeGen/RegisterPressure.h"
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#include "llvm/CodeGen/ResourcePriorityQueue.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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namespace llvm {
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//===----------------------------------------------------------------------===//
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// ConvergingVLIWScheduler - Implementation of the standard
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// MachineSchedStrategy.
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//===----------------------------------------------------------------------===//
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class VLIWResourceModel {
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/// ResourcesModel - Represents VLIW state.
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/// Not limited to VLIW targets per say, but assumes
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/// definition of DFA by a target.
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DFAPacketizer *ResourcesModel;
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const TargetSchedModel *SchedModel;
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/// Local packet/bundle model. Purely
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/// internal to the MI schedulre at the time.
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std::vector<SUnit*> Packet;
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/// Total packets created.
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unsigned TotalPackets;
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public:
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VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
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: SchedModel(SM), TotalPackets(0) {
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ResourcesModel = STI.getInstrInfo()->CreateTargetScheduleState(STI);
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// This hard requirement could be relaxed,
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// but for now do not let it proceed.
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assert(ResourcesModel && "Unimplemented CreateTargetScheduleState.");
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Packet.resize(SchedModel->getIssueWidth());
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Packet.clear();
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ResourcesModel->clearResources();
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}
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~VLIWResourceModel() {
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delete ResourcesModel;
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}
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void resetPacketState() {
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Packet.clear();
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}
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void resetDFA() {
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ResourcesModel->clearResources();
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}
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void reset() {
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Packet.clear();
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ResourcesModel->clearResources();
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}
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bool isResourceAvailable(SUnit *SU);
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bool reserveResources(SUnit *SU);
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unsigned getTotalPackets() const { return TotalPackets; }
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};
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/// Extend the standard ScheduleDAGMI to provide more context and override the
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/// top-level schedule() driver.
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class VLIWMachineScheduler : public ScheduleDAGMILive {
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public:
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VLIWMachineScheduler(MachineSchedContext *C,
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std::unique_ptr<MachineSchedStrategy> S)
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: ScheduleDAGMILive(C, std::move(S)) {}
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/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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void schedule() override;
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/// Perform platform-specific DAG postprocessing.
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void postprocessDAG();
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};
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/// ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics
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/// to balance the schedule.
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class ConvergingVLIWScheduler : public MachineSchedStrategy {
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/// Store the state used by ConvergingVLIWScheduler heuristics, required
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/// for the lifetime of one invocation of pickNode().
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struct SchedCandidate {
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// The best SUnit candidate.
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SUnit *SU;
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// Register pressure values for the best candidate.
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RegPressureDelta RPDelta;
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// Best scheduling cost.
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int SCost;
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SchedCandidate(): SU(nullptr), SCost(0) {}
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};
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/// Represent the type of SchedCandidate found within a single queue.
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enum CandResult {
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NoCand, NodeOrder, SingleExcess, SingleCritical, SingleMax, MultiPressure,
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BestCost};
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/// Each Scheduling boundary is associated with ready queues. It tracks the
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/// current cycle in whichever direction at has moved, and maintains the state
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/// of "hazards" and other interlocks at the current cycle.
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struct VLIWSchedBoundary {
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VLIWMachineScheduler *DAG;
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const TargetSchedModel *SchedModel;
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ReadyQueue Available;
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ReadyQueue Pending;
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bool CheckPending;
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ScheduleHazardRecognizer *HazardRec;
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VLIWResourceModel *ResourceModel;
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unsigned CurrCycle;
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unsigned IssueCount;
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/// MinReadyCycle - Cycle of the soonest available instruction.
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unsigned MinReadyCycle;
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// Remember the greatest min operand latency.
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unsigned MaxMinLatency;
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/// Pending queues extend the ready queues with the same ID and the
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/// PendingFlag set.
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VLIWSchedBoundary(unsigned ID, const Twine &Name):
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DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"),
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Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name+".P"),
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CheckPending(false), HazardRec(nullptr), ResourceModel(nullptr),
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CurrCycle(0), IssueCount(0),
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MinReadyCycle(UINT_MAX), MaxMinLatency(0) {}
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~VLIWSchedBoundary() {
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delete ResourceModel;
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delete HazardRec;
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}
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void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) {
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DAG = dag;
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SchedModel = smodel;
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}
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bool isTop() const {
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return Available.getID() == ConvergingVLIWScheduler::TopQID;
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}
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bool checkHazard(SUnit *SU);
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void releaseNode(SUnit *SU, unsigned ReadyCycle);
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void bumpCycle();
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void bumpNode(SUnit *SU);
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void releasePending();
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void removeReady(SUnit *SU);
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SUnit *pickOnlyChoice();
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};
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VLIWMachineScheduler *DAG;
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const TargetSchedModel *SchedModel;
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// State of the top and bottom scheduled instruction boundaries.
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VLIWSchedBoundary Top;
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VLIWSchedBoundary Bot;
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public:
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/// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
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enum {
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TopQID = 1,
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BotQID = 2,
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LogMaxQID = 2
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};
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ConvergingVLIWScheduler()
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: DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"),
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Bot(BotQID, "BotQ") {}
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void initialize(ScheduleDAGMI *dag) override;
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SUnit *pickNode(bool &IsTopNode) override;
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void schedNode(SUnit *SU, bool IsTopNode) override;
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void releaseTopNode(SUnit *SU) override;
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void releaseBottomNode(SUnit *SU) override;
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unsigned ReportPackets() {
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return Top.ResourceModel->getTotalPackets() +
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Bot.ResourceModel->getTotalPackets();
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}
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protected:
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SUnit *pickNodeBidrectional(bool &IsTopNode);
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int SchedulingCost(ReadyQueue &Q,
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SUnit *SU, SchedCandidate &Candidate,
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RegPressureDelta &Delta, bool verbose);
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CandResult pickNodeFromQueue(ReadyQueue &Q,
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const RegPressureTracker &RPTracker,
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SchedCandidate &Candidate);
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#ifndef NDEBUG
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void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU,
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PressureChange P = PressureChange());
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#endif
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};
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} // namespace
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#endif
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