forked from OSchip/llvm-project
316 lines
10 KiB
C++
316 lines
10 KiB
C++
//===-- SystemZTargetTransformInfo.cpp - SystemZ-specific TTI -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a TargetTransformInfo analysis pass specific to the
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// SystemZ target machine. It uses the target's detailed information to provide
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// more precise answers to certain TTI queries, while letting the target
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// independent and default TTI implementations handle the rest.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZTargetTransformInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "systemztti"
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//===----------------------------------------------------------------------===//
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//
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// SystemZ cost model.
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//
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//===----------------------------------------------------------------------===//
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int SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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// There is no cost model for constants with a bit size of 0. Return TCC_Free
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// here, so that constant hoisting will ignore this constant.
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if (BitSize == 0)
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return TTI::TCC_Free;
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// No cost model for operations on integers larger than 64 bit implemented yet.
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if (BitSize > 64)
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return TTI::TCC_Free;
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if (Imm == 0)
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return TTI::TCC_Free;
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if (Imm.getBitWidth() <= 64) {
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// Constants loaded via lgfi.
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if (isInt<32>(Imm.getSExtValue()))
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return TTI::TCC_Basic;
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// Constants loaded via llilf.
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if (isUInt<32>(Imm.getZExtValue()))
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return TTI::TCC_Basic;
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// Constants loaded via llihf:
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if ((Imm.getZExtValue() & 0xffffffff) == 0)
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return TTI::TCC_Basic;
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return 2 * TTI::TCC_Basic;
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}
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return 4 * TTI::TCC_Basic;
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}
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int SystemZTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx,
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const APInt &Imm, Type *Ty) {
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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// There is no cost model for constants with a bit size of 0. Return TCC_Free
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// here, so that constant hoisting will ignore this constant.
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if (BitSize == 0)
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return TTI::TCC_Free;
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// No cost model for operations on integers larger than 64 bit implemented yet.
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if (BitSize > 64)
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return TTI::TCC_Free;
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switch (Opcode) {
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default:
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return TTI::TCC_Free;
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case Instruction::GetElementPtr:
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// Always hoist the base address of a GetElementPtr. This prevents the
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// creation of new constants for every base constant that gets constant
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// folded with the offset.
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if (Idx == 0)
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return 2 * TTI::TCC_Basic;
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return TTI::TCC_Free;
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case Instruction::Store:
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if (Idx == 0 && Imm.getBitWidth() <= 64) {
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// Any 8-bit immediate store can by implemented via mvi.
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if (BitSize == 8)
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return TTI::TCC_Free;
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// 16-bit immediate values can be stored via mvhhi/mvhi/mvghi.
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if (isInt<16>(Imm.getSExtValue()))
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return TTI::TCC_Free;
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}
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break;
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case Instruction::ICmp:
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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// Comparisons against signed 32-bit immediates implemented via cgfi.
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if (isInt<32>(Imm.getSExtValue()))
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return TTI::TCC_Free;
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// Comparisons against unsigned 32-bit immediates implemented via clgfi.
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if (isUInt<32>(Imm.getZExtValue()))
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return TTI::TCC_Free;
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}
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break;
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case Instruction::Add:
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case Instruction::Sub:
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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// We use algfi/slgfi to add/subtract 32-bit unsigned immediates.
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if (isUInt<32>(Imm.getZExtValue()))
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return TTI::TCC_Free;
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// Or their negation, by swapping addition vs. subtraction.
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if (isUInt<32>(-Imm.getSExtValue()))
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return TTI::TCC_Free;
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}
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break;
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case Instruction::Mul:
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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// We use msgfi to multiply by 32-bit signed immediates.
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if (isInt<32>(Imm.getSExtValue()))
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return TTI::TCC_Free;
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}
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break;
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case Instruction::Or:
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case Instruction::Xor:
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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// Masks supported by oilf/xilf.
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if (isUInt<32>(Imm.getZExtValue()))
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return TTI::TCC_Free;
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// Masks supported by oihf/xihf.
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if ((Imm.getZExtValue() & 0xffffffff) == 0)
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return TTI::TCC_Free;
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}
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break;
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case Instruction::And:
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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// Any 32-bit AND operation can by implemented via nilf.
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if (BitSize <= 32)
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return TTI::TCC_Free;
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// 64-bit masks supported by nilf.
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if (isUInt<32>(~Imm.getZExtValue()))
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return TTI::TCC_Free;
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// 64-bit masks supported by nilh.
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if ((Imm.getZExtValue() & 0xffffffff) == 0xffffffff)
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return TTI::TCC_Free;
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// Some 64-bit AND operations can be implemented via risbg.
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const SystemZInstrInfo *TII = ST->getInstrInfo();
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unsigned Start, End;
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if (TII->isRxSBGMask(Imm.getZExtValue(), BitSize, Start, End))
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return TTI::TCC_Free;
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}
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break;
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case Instruction::Shl:
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case Instruction::LShr:
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case Instruction::AShr:
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// Always return TCC_Free for the shift value of a shift instruction.
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if (Idx == 1)
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return TTI::TCC_Free;
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break;
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case Instruction::UDiv:
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case Instruction::SDiv:
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case Instruction::URem:
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case Instruction::SRem:
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case Instruction::Trunc:
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case Instruction::ZExt:
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case Instruction::SExt:
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case Instruction::IntToPtr:
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case Instruction::PtrToInt:
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case Instruction::BitCast:
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case Instruction::PHI:
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case Instruction::Call:
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case Instruction::Select:
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case Instruction::Ret:
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case Instruction::Load:
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break;
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}
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return SystemZTTIImpl::getIntImmCost(Imm, Ty);
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}
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int SystemZTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
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const APInt &Imm, Type *Ty) {
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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// There is no cost model for constants with a bit size of 0. Return TCC_Free
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// here, so that constant hoisting will ignore this constant.
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if (BitSize == 0)
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return TTI::TCC_Free;
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// No cost model for operations on integers larger than 64 bit implemented yet.
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if (BitSize > 64)
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return TTI::TCC_Free;
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switch (IID) {
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default:
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return TTI::TCC_Free;
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case Intrinsic::sadd_with_overflow:
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case Intrinsic::uadd_with_overflow:
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case Intrinsic::ssub_with_overflow:
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case Intrinsic::usub_with_overflow:
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// These get expanded to include a normal addition/subtraction.
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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if (isUInt<32>(Imm.getZExtValue()))
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return TTI::TCC_Free;
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if (isUInt<32>(-Imm.getSExtValue()))
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return TTI::TCC_Free;
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}
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break;
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case Intrinsic::smul_with_overflow:
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case Intrinsic::umul_with_overflow:
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// These get expanded to include a normal multiplication.
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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if (isInt<32>(Imm.getSExtValue()))
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return TTI::TCC_Free;
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}
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break;
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case Intrinsic::experimental_stackmap:
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if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
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return TTI::TCC_Free;
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break;
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case Intrinsic::experimental_patchpoint_void:
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case Intrinsic::experimental_patchpoint_i64:
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if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
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return TTI::TCC_Free;
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break;
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}
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return SystemZTTIImpl::getIntImmCost(Imm, Ty);
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}
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TargetTransformInfo::PopcntSupportKind
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SystemZTTIImpl::getPopcntSupport(unsigned TyWidth) {
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assert(isPowerOf2_32(TyWidth) && "Type width must be power of 2");
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if (ST->hasPopulationCount() && TyWidth <= 64)
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return TTI::PSK_FastHardware;
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return TTI::PSK_Software;
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}
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void SystemZTTIImpl::getUnrollingPreferences(Loop *L,
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TTI::UnrollingPreferences &UP) {
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// Find out if L contains a call, what the machine instruction count
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// estimate is, and how many stores there are.
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bool HasCall = false;
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unsigned NumStores = 0;
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for (auto &BB : L->blocks())
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for (auto &I : *BB) {
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if (isa<CallInst>(&I) || isa<InvokeInst>(&I)) {
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ImmutableCallSite CS(&I);
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if (const Function *F = CS.getCalledFunction()) {
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if (isLoweredToCall(F))
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HasCall = true;
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if (F->getIntrinsicID() == Intrinsic::memcpy ||
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F->getIntrinsicID() == Intrinsic::memset)
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NumStores++;
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} else { // indirect call.
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HasCall = true;
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}
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}
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if (isa<StoreInst>(&I)) {
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NumStores++;
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Type *MemAccessTy = I.getOperand(0)->getType();
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if((MemAccessTy->isIntegerTy() || MemAccessTy->isFloatingPointTy()) &&
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(getDataLayout().getTypeSizeInBits(MemAccessTy) == 128))
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NumStores++; // 128 bit fp/int stores get split.
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}
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}
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// The z13 processor will run out of store tags if too many stores
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// are fed into it too quickly. Therefore make sure there are not
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// too many stores in the resulting unrolled loop.
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unsigned const Max = (NumStores ? (12 / NumStores) : UINT_MAX);
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if (HasCall) {
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// Only allow full unrolling if loop has any calls.
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UP.FullUnrollMaxCount = Max;
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UP.MaxCount = 1;
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return;
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}
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UP.MaxCount = Max;
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if (UP.MaxCount <= 1)
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return;
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// Allow partial and runtime trip count unrolling.
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UP.Partial = UP.Runtime = true;
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UP.PartialThreshold = 75;
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UP.DefaultUnrollRuntimeCount = 4;
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// Allow expensive instructions in the pre-header of the loop.
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UP.AllowExpensiveTripCount = true;
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UP.Force = true;
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}
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unsigned SystemZTTIImpl::getNumberOfRegisters(bool Vector) {
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if (!Vector)
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// Discount the stack pointer. Also leave out %r0, since it can't
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// be used in an address.
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return 14;
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if (ST->hasVector())
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return 32;
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return 0;
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}
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unsigned SystemZTTIImpl::getRegisterBitWidth(bool Vector) {
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if (!Vector)
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return 64;
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if (ST->hasVector())
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return 128;
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return 0;
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}
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