forked from OSchip/llvm-project
70 lines
2.2 KiB
LLVM
70 lines
2.2 KiB
LLVM
; XFAIL: *
|
|
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
|
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
|
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
|
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
|
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
|
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
@glob = common local_unnamed_addr global i32 0, align 4
|
|
|
|
define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
|
|
; CHECK-LABEL: test_igesi:
|
|
; CHECK: # BB#0: # %entry
|
|
; CHECK-NEXT: sub r3, r3, r4
|
|
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
|
; CHECK-NEXT: xori r3, r3, 1
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%cmp = icmp sge i32 %a, %b
|
|
%conv = zext i1 %cmp to i32
|
|
ret i32 %conv
|
|
}
|
|
|
|
define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
|
|
; CHECK-LABEL: test_igesi_sext:
|
|
; CHECK: # BB#0: # %entry
|
|
; CHECK-NEXT: sub r3, r3, r4
|
|
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
|
; CHECK-NEXT: addi r3, r3, -1
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%cmp = icmp sge i32 %a, %b
|
|
%sub = sext i1 %cmp to i32
|
|
ret i32 %sub
|
|
}
|
|
|
|
define void @test_igesi_store(i32 signext %a, i32 signext %b) {
|
|
; CHECK-LABEL: test_igesi_store:
|
|
; CHECK: # BB#0: # %entry
|
|
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
|
; CHECK-NEXT: sub r3, r3, r4
|
|
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
|
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
|
; CHECK-NEXT: xori r3, r3, 1
|
|
; CHECK-NEXT: stw r3, 0(r12)
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%cmp = icmp sge i32 %a, %b
|
|
%conv = zext i1 %cmp to i32
|
|
store i32 %conv, i32* @glob, align 4
|
|
ret void
|
|
}
|
|
|
|
define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
|
|
; CHECK-LABEL: test_igesi_sext_store:
|
|
; CHECK: # BB#0: # %entry
|
|
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
|
; CHECK-NEXT: sub r3, r3, r4
|
|
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
|
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
|
; CHECK-NEXT: addi r3, r3, -1
|
|
; CHECK-NEXT: stw r3, 0(r12)
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%cmp = icmp sge i32 %a, %b
|
|
%sub = sext i1 %cmp to i32
|
|
store i32 %sub, i32* @glob, align 4
|
|
ret void
|
|
}
|