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llvm-project/llvm/test/CodeGen
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Matt Arsenault cf9b6d8d57 AMDGPU: Fix missing gfx9 atomic inc/dec tests 
The global instructions weren't tested. Plus there
were also some -enable-var-scope violations and
broken check prefixes.

llvm-svn: 318003
 		2017-11-12 23:40:12 +00:00
..
AArch64 [globalisel][tablegen] Import signextload and zeroextload. 2017-11-11 03:23:44 +00:00
AMDGPU AMDGPU: Fix missing gfx9 atomic inc/dec tests 2017-11-12 23:40:12 +00:00
ARC
…
ARM [GlobalISel] Enable legalizing non-power-of-2 sized types. 2017-11-07 10:34:34 +00:00
AVR [AVR] Fix the select-mbb-placement-bug.ll 2017-10-20 04:17:14 +00:00
BPF bpf: fix bug on silently truncating 64-bit immediate 2017-10-16 04:14:53 +00:00
Generic Add an @llvm.sideeffect intrinsic 2017-11-08 21:59:51 +00:00
Hexagon [Hexagon] Prefer L2_loadrub_io over L4_loadrub_rr 2017-11-02 21:56:59 +00:00
Inputs
…
Lanai MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
MIR [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
MSP430
…
Mips [mips] Correct microMIP's jump and add unconditional branch pseudo 2017-11-09 16:02:18 +00:00
NVPTX [NVPTX] Implement __nvvm_atom_add_gen_d builtin. 2017-11-07 22:10:54 +00:00
Nios2
…
PowerPC Use new vector insert half-word and byte instructions when we see insertelement on '8 x i16' and '16 x i8' types. Also extended existing lit testcase to cover these cases. 2017-11-07 20:55:43 +00:00
RISCV [RISCV] Re-generate test/CodeGen/RISCV/alu32.ll using update_llc_test_checks.py 2017-11-09 15:45:42 +00:00
SPARC Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"" 2017-10-03 16:59:13 +00:00
SystemZ [RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints. 2017-11-10 08:46:26 +00:00
Thumb [ARM] Dynamic stack alignment for 16-bit Thumb 2017-10-22 11:56:35 +00:00
Thumb2 [ARM] Honor -mfloat-abi for libcall calling convention 2017-10-26 21:42:32 +00:00
WebAssembly [WebAssembly] Fix stack offsets of return values from call lowering. 2017-11-10 16:26:04 +00:00
WinEH Make x86 __ehhandler comdat if parent function is 2017-10-20 17:04:43 +00:00
X86 [X86] Add an X86ISD::RANGES opcode to use for the scalar intrinsics. 2017-11-12 18:51:09 +00:00
XCore [MC] Suppress .Lcfi labels when emitting textual assembly 2017-10-10 00:57:36 +00:00