forked from OSchip/llvm-project
150 lines
5.7 KiB
ArmAsm
150 lines
5.7 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate out of lower bound [-8, 7].
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st1d z25.d, p4, [x16, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: st1d z25.d, p4, [x16, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Immediate out of upper bound [-8, 7].
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st1d z16.d, p4, [x2, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: st1d z16.d, p4, [x2, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Restricted predicate has range [0, 7].
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st1d z12.d, p8, [x4, #14, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
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// CHECK-NEXT: st1d z12.d, p8, [x4, #14, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list
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st1d { }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: st1d { }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d { z1.d, z2.d }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: st1d { z1.d, z2.d }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d { v0.2d }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: st1d { v0.2d }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
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st1d z0.d, p0, [x0, x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, xzr]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, xzr]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, x0, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, x0, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, w0, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, w0, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + vector addressing modes
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st1d z0.d, p0, [x0, z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: st1d z0.d, p0, [x0, z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, z0.d, uxtw #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, uxtw #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, z0.d, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, z0.d, lsl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
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// CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector + immediate addressing modes
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st1d z0.s, p0, [z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: st1d z0.s, p0, [z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.s, p0, [z0.s, #8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: st1d z0.s, p0, [z0.s, #8]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [z0.d, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
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// CHECK-NEXT: st1d z0.d, p0, [z0.d, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [z0.d, #-8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
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// CHECK-NEXT: st1d z0.d, p0, [z0.d, #-8]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [z0.d, #249]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
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// CHECK-NEXT: st1d z0.d, p0, [z0.d, #249]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [z0.d, #256]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
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// CHECK-NEXT: st1d z0.d, p0, [z0.d, #256]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [z0.d, #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
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// CHECK-NEXT: st1d z0.d, p0, [z0.d, #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p7/z, z6.d
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st1d { z31.d }, p7, [z31.d, #248]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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st1d { z31.d }, p7, [z31.d, #248]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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