forked from OSchip/llvm-project
34 lines
1.1 KiB
ArmAsm
34 lines
1.1 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Tied operands must match
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fmulx z0.h, p7/m, z1.h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: fmulx z0.h, p7/m, z1.h, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element widths.
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fmulx z0.b, p7/m, z0.b, z31.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmulx z0.b, p7/m, z0.b, z31.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmulx z0.h, p7/m, z0.h, z31.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmulx z0.h, p7/m, z0.h, z31.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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fmulx z0.h, p8/m, z0.h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
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// CHECK-NEXT: fmulx z0.h, p8/m, z0.h, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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