forked from OSchip/llvm-project
28 lines
1.0 KiB
ArmAsm
28 lines
1.0 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Predicate register must have .b suffix
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ands p0.h, p0/z, p0.h, p1.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
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// CHECK-NEXT: ands p0.h, p0/z, p0.h, p1.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ands p0.s, p0/z, p0.s, p1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
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// CHECK-NEXT: ands p0.s, p0/z, p0.s, p1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ands p0.d, p0/z, p0.d, p1.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
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// CHECK-NEXT: ands p0.d, p0/z, p0.d, p1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Operation only has zeroing predicate behaviour (p0/z).
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ands p0.b, p0/m, p1.b, p2.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: ands p0.b, p0/m, p1.b, p2.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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